Sci Baud Rate Register: Low (Scix_Bdl) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI
baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supply
current. When BR is 1 - 8191, the SCI baud rate equals BUSCLK/(16×BR).

22.4.2 SCI Baud Rate Register: Low (SCIx_BDL)

This register, along with SCI_BDH, control the prescale divisor for SCI baud rate
generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to
SCI_BDH to buffer the high half of the new value and then write to SCI_BDL. The
working value in SCI_BDH does not change until SCI_BDL is written.
SCI_BDL is reset to a non-zero value, so after reset the baud rate generator remains
disabled until the first time the receiver or transmitter is enabled; that is, SCI_C2[RE] or
SCI_C2[TE] bits are written to 1.
Address: 1868h base + 1h offset = 1869h
Bit 7
Read
Write
Reset
0
Field
SBR Baud Rate Modulo Divisor
These 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the SCI
baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supply
current. When BR is 1 - 8191, the SCI baud rate equals BUSCLK/(16×BR).
22.4.3 SCI Control Register 1 (SCIx_C1)
This read/write register controls various optional features of the SCI system.
Address: 1868h base + 2h offset = 186Ah
Bit 7
Read
LOOPS
Write
Reset
0
NXP Semiconductors
SCIx_BDH field descriptions (continued)
6 5
0 0
SCIx_BDL field descriptions
6 5
SCISWAI RSRC
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 22 Serial Communications Interface (SCI)
Description
4 3
SBR
0 0
Description
4 3
M WAKE ILT
0 0
2 1
1 0
2 1
PE PT
0 0
0
0
0
0
401