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Generator loading
Up/Down
Counter
Reload
Change
Reload
Frequency
26.3.8.3 Reload flag
At every reload opportunity the PWM reload flag (PWMF) bit in the CTRL register is set
regardless of the state of the LDOK bit. If the PWM reload interrupt enable (PWMRIE)
bit is set, the PWMF flag generates a core interrupt request allowing software to calculate
new PWM parameters in real time. When PWMRIE is not set, reloads still occur at the
selected reload rate without generating interrupt requests. Clear the PWMF bit by reading
it then write a 0 to it.
Up/Down
Counter
LDOK = 1
Modulus = 3
PWM Value= 1
PWMF = 1
PWM
Figure 26-20. Full-Cycle center-aligned PWM value loading
Up/Down
Counter
LDOK = 1
Modulus = 2
PWM Value = 1
PWMF = 1
PWM
Figure 26-21. Full-Cycle center-aligned modulus loading
498
To Every
Two Opportunities
Figure 26-19. Half cycle reload frequency change
Half = 0, LDFQ[3:0] = 0000 = Reload Every Cycle
0
3
2
1
Half = 0, LDFQ[3:0] = 0000 = Reload Every Cycle
2
1
0
1
3
1
1
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
To Every
Four Opportunities
1
3
2
1
3
2
2
1
1
1
0
1
2
1
1
To Every
Opportunity
0
3
1
1
1
1
0
0
0
0
1
2
1
1
1
1
1
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