Latency Issues - NXP Semiconductors MC9S08SU16 Reference Manual

CMP Functional Description
If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the
sample input. The output state of the filter changes when CR0[FILTER_CNT]
consecutive samples all agree that the output value has changed.

18.11.4.2 Latency Issues

The FPR[FILT_PER] value (or SAMPLE period) should be set such that the sampling
period is just larger than the period of the expected noise. This way a noise spike will
only corrupt one sample. The CR0[FILTER_CNT] value should be chosen to reduce the
probability of noisy samples causing an incorrect transition to be recognized. The
probability of an incorrect transition is defined as the probability of an incorrect sample
raised to the CR0[FILTER_CNT] power.
The following table summarizes maximum latency values for the various modes of
operation in the absence of noise. Filtering latency is restarted each time an actual output
transition is masked by noise.
The values of FPR[FILT_PER] (or SAMPLE period) and CR0[FILTER_CNT] must also
be traded off against the desire for minimal latency in recognizing actual comparator
output transitions. The probability of detecting an actual output change within the
nominal latency is the probability of a correct sample raised to the CR0[FILTER_CNT]
power.
Table 18-3. Comparator Sample/Filter Maximum Latencies
CR1[ CR1[ CR1[
Mode #
EN] WE]
1 0 X
2A 1 0
2B 1 0
3A 1 0
3B 1 0
4A 1 0
4B 1 0
5A 1 1
5B 1 1
6 1 1
7 1 1
314
CR0[FILTER FPR[FILT_P
SE] _CNT] ER]
X X
0 0x00
0 X 0x00
1 0x01
0 0x01 > 0x00
1 > 0x01
0 > 0x01 > 0x00
0 0x00
0 X 0x00
0 0x01 0x01 - 0xFF
0 > 0x01 0x01 - 0xFF
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Operation
X Disabled
X Continuous Mode
X Sampled, Non-Filtered mode
X Sampled, Filtered mode
X Windowed mode
Windowed / Resampled
mode
Windowed / Filtered mode
1
Maximum Latency
N/A
T
PD
T + T + T
PD SAMPLE per
T + (FPR[FILT_PER] x
PD
T ) + T
per per
T + (CR0[FILTER_CNT] x
PD
T ) + T
SAMPLE per
T + (CR0[FILTER_CNT] x
PD
FPR[FILT_PER] x T ) + T
per per
T + T
PD per
T + T
PD per
T + (FPR[FILT_PER] x
PD
T ) + 2T
per per
T + (CR0[FILTER_CNT] x
PD
FPR[FILT_PER] x T ) +
per
2T
per
NXP Semiconductors