Chip Specific Programmable Delay Block - NXP Semiconductors MC9S08SU16 Reference Manual

Chapter 23
Programmable Delay Block (PDB)

23.1 Chip specific programmable delay block

This device has one programmable delay block (PDB)
The PDB is used to synchronize between PWM sync pulse and ADC samples or
comparator sampling windows. The primary function of the programmable delay block is
simply to provide a controllable delay from a trigger signal . The module includes two
timebase. Each has its own counter and one comparator against the counter. Its operation
modes include single shot or continuous mode. The input and output of PDBs are
connected through intermodule crossbar to other modules, such as PWM, ADCs,
Comparators.
Customization:
• Primary clock: HSCLK (up to 40 MHz)
• Alternate clock: No
• The following table summarizes the signal connection of PDB modules.
Module
PDB0
PDB1
NXP Semiconductors
Table 23-1. PDB module signals
Connection
PDB0 HW Trigger
PDB0 Output
Internal Clock
PDB1 HW trigger
PDB1 OUTPUT
Internal Clock
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Signal Connect to
XBAR_OUT8
XBAR_IN8
HSCLK
XBAR_OUT9
XBAR_IN9
HSCLK
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