NXP Semiconductors MC9S12VRP64 Manuals

Manuals and User Guides for NXP Semiconductors MC9S12VRP64. We have 1 NXP Semiconductors MC9S12VRP64 manual available for free PDF download: Owner Reference Manual

NXP Semiconductors MC9S12VRP64 Owner Reference Manual

NXP Semiconductors MC9S12VRP64 Owner Reference Manual (555 pages)

MC9S12VRP Series S12 MagniV Microcontrollers

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Table of Contents

Table of Contents
3
Introduction
17
Features
18
Chip-Level Features
19
Module Features
20
Chapter 1

21
- On-Chip SRAM
  21
- System Integrity Support
  22
- Analog-To-Digital Converter Module (ADC)
  23
- Low-Side Driver (LSDRV)
  24
- Debugger (DBG)
  25
- Family Memory Map
  26
  - Part ID Assignments
    29
  - Power Supply Pins
    32
  - Device Pinouts
    34
  - MC9S12VRP Pinout 48-Pin LQFP
    35
  - Modes of Operation
    39
- Security
  40
  - Interrupt Vectors
    41
  - Effects of Reset
    43
  - ADC Special Conversion Channels
    44
  - CPMU High Temperature Trimming
    45
Chapter 2

47
- Introduction
  48
- Features
  50
- External Signal Description
  51
- Memory Map and Register Definition
  56
- Register Map
  57
- Device Specific PIM Registers
  61
- PIM Generic Registers
  68
- PIM Generic Register Exceptions
  74
- Functional Description
  82
- Registers
  83
- Pull Devices
  85
- High-Voltage Input
  87
- Initialization and Application Information
  89
  - Over-Current Protection on PP2 and PP0
    90
    
    Introduction
    93
    
    Features
    94
    
    External Signal Description
    95
    
    Register Descriptions
    96
    
    Functional Description
    100
  - Unimplemented and Reserved Address Ranges
    104
  - Prioritization of Memory Accesses
    105
    
    Introduction
    107
    
    Features
    108
    
    Modes of Operation
    110
Chapter 4 S12CPMU_UHV_V8 Block Diagram

113
- Signal Description
  115
- VSS— Ground Pin
  116
- Memory Map and Registers
  117
  - Register Descriptions
    119
  - Functional Description
    153
  - Startup from Reset
    155
  - Stop Mode Using PLLCLK as Source of the Bus Clock
    156
  - External Oscillator
    158
  - System Clock Configurations
    159
  - Resets
    160
  - Description of Reset Operation
    161
  - Oscillator Clock Monitor Reset
    162
  - Power-On Reset (POR)
    164
  - Description of Interrupt Operation
    165
    
    Initialization/Application Information
    166
    
    MC9S12VRP Family Reference Manual Rev. 1.3 NXP Semiconductors
    167
    
    Introduction
    169
    
    Modes of Operation
    170
    
    Block Diagram
    171
    
    Register Descriptions
    172
Chapter 5

176
- Family ID Assignment
  176
- BDM Hardware Commands
  177
- Standard BDM Firmware Commands
  178
- BDM Command Structure
  179
- BDM Serial Interface
  181
- Serial Interface Hardware Handshake Protocol
  184
- Hardware Handshake Abort Procedure
  186
- SYNC — Request Timed Reference Pulse
  189
- Serial Communication Time out
  190
- Introduction
  193
Chapter 6

194
- Overview
  194
  - Modes of Operation
    195
  - External Signal Description
    196
  - Register Descriptions
    197
  - Functional Description
    214
- Comparator Modes
  215
- Match Modes (Forced or Tagged)
  219
- State Sequence Control
  220
- Trace Buffer Operation
  221
- Tagging
  227
- Breakpoints
  228
- Application Information
  230
- Scenario 3
  231
- Scenario 5
  233
- Scenario 8
  234
  - Introduction
    237
  - Modes of Operation
    238
  - External Signal Description
    239
  - Functional Description
    240
Chapter 7

241
- Reset Exception Requests
  241
- Initialization/Application Information
  242
  - Introduction
    245
  - Modes of Operation
    247
  - Block Diagram
    248
  - Signal Description
    249
  - Register Descriptions
    252
  - Functional Description
    268
  - Resets
    270
  - Introduction
    271
  - Block Diagram
    272
  - PWM7 - PWM0 — PWM Channel 7 - 0
    273
  - Functional Description
    287
Chapter 9 PWM Channel Timers

291
- Resets
  299
  - Interrupts
    300
  - Introduction
    301
  - Features
    302
  - Block Diagram
    303
  - External Signal Description
    304
  - Register Descriptions
    305
  - Functional Description
    317
  - Infrared Interface Submodule
    318
  - Data Format
    319
  - Baud Rate Generation
    320
  - Transmitter
    321
  - Receiver
    326
  - Single-Wire Operation
    334
  - Loop Operation
    335
  - Modes of Operation
    336
  - Recovery from Wait Mode
    339
    
    Introduction
    341
    
    Block Diagrams
    342
Chapter 10 Memory Map and Register Definition

343
- Functional Description
  354
Chapter 11

355
- Prescaler
  355
- Input Capture
  356
- Resets
  357
  - Introduction
    359
  - Modes of Operation
    360
  - External Signal Description
    361
  - Memory Map and Register Definition
    362
  - Register Definition
    363
  - HSDRV2C Slew Rate Control Register (HSSLR)
    365
  - Reserved Register
    366
  - HSDRV2C Status Register (HSSR)
    367
  - HSDRV2C Interrupt Enable Register (HSIE)
    368
  - HSDRV2C Interrupt Flag Register (HSIF)
    369
  - Over-Current Shutdown
    370
    
    Introduction
    371
    
    Modes of Operation
    372
- External Signal Description
  373
Chapter 13

375
- Register Definition
  375
- LSDRV Configuration Register (LSCR)
  376
- Reserved Register
  377
- LSDRV Status Register (LSSR)
  378
- LSDRV Interrupt Enable Register (LSIE)
  379
- LSDRV Interrupt Flag Register (LSIF)
  380
- Functional Description
  381
- Introduction
  383
  - Block Diagram
    384
- External Signal Description
  385
  - Register Definition
    387
  - LS2DRV Configuration Register (LS2CR)
    388
  - Reserved Register
    389
  - LS2DRV Interrupt Enable Register (LS2IE)
    390
  - LS2DRV Interrupt Flag Register (LS2IF)
    391
- Functional Description
  392
Chapter 17

393
- Features
  393
- Block Diagram
  394
- Memory Map and Register Definition
  395
  - Functional Description
    400
  - Interrupts
    402
  - Introduction
    403
  - Modes of Operation
    404
- External Signal Description
  406
- Memory Map and Register Definition
  407
  - Register Descriptions
    408
- Functional Description
  415
  - Modes
    416
  - Interrupts
    419
- Application Information
  422
- Introduction
  425
Chapter 15 Block Diagram

426
- VSUP — Voltage Supply Pin
  427
- Register Descriptions
  428
  - Functional Description
    433
  - Interrupts
    434
Chapter 18

437
- Introduction
  438
- Features
  439
- External Signal Description
  440
- Memory Map and Registers
  441
  - Register Descriptions
    445
  - Functional Description
    464
  - Allowed Simultaneous P-Flash and D-Flash Operations
    469
  - Flash Command Description
    470
  - Interrupts
    484
  - Wait Mode
    485
  - Unsecuring the MCU in Special Single Chip Mode Using BDM
    486
  - Mode and Security Effects on Flash Command Availability
    487
- A.1 General
  489
Appendix A

490
Appendix B

503
Appendix C

512
- C.3.1 ADC Accuracy Definitions
  512
Appendix D

515
- D.1 Static Characteristics
  515
- D.2 Dynamic Characteristics
  516
Appendix E

517
- E.1 Static Electrical Characteristics
  517
- E.2 Dynamic Electrical Characteristics
  518
  - F.1 LSDRV Static Characteristics
    520
  - F.2 LSDRV Dynamic Characteristics
    521
Appendix F

522
Appendix G Appendix J

529
Package Information

530
- Package Information
  531
- Package Information
  532
Appendix K

533
Ordering Information

534
Appendix L

535

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