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Chapter 10 Central processor unit
10.5 HCS08 V6 Opcodes
The HCS08 V6 Core has 254 one-byte opcodes and 47 two-byte opcodes, totaling 301
opcodes. For a more detailed description of the HCS08 V6 instructions please refer to the
Instruction Set Summary section.
10.6 Special Operations
The CPU performs a few special operations that are similar to instructions but do not
have opcodes like other CPU instructions. This section provides additional information
about these operations.
10.6.1 Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the
COP (computer operating properly) watchdog, or by assertion of an external active-low
reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the
MCU does not wait for an instruction boundary before responding to a reset event).
The reset event is considered concluded when the sequence to determine whether the
reset came from an internal source is done and when the reset pin is no longer asserted.
At the conclusion of a reset event, the CPU performs a 6-cycle sequence to fetch the reset
vector from $FFFE and $FFFF and to fill the instruction queue in preparation for
execution of the first program instruction.
10.6.2 Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before
responding to the interrupt. At this point, the program counter is pointing at the start of
the next instruction, which is where the CPU should return after servicing the interrupt.
The CPU responds to an interrupt by performing the same sequence of operations as for a
software interrupt (SWI) instruction, except the address used for the vector fetch is
determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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