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12.4.1.5 FLL bypassed external (FBE)
The FLL bypassed external (FBE) mode is entered when all the following conditions
occur:
• 10b is written to ICS_C1[CLKS].
• 0b is written to ICS_C1[IREFS].
• ICS_C1[RDIV] and SIM_SOPT1[RANGE] fields are written to divide external
reference clock to be within the range of 31.25 kHz to 39.0625 kHz.
• BDM mode is active or 0b is written to C2[LP].
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference
clock source. The FLL clock is controlled by the external reference clock, and the FLL
loop locks the FLL frequency to 1024 times the external reference frequency, as selected
by ICS_C1[RDIV] and SIM_SOPT1[RANGE], the external reference clock is enabled.
12.4.1.6 FLL bypassed external low power (FBELP)
The FLL bypassed external low-power (FBELP) mode is entered when all the following
conditions occur:
• 10b is written to ICS_C1[CLKS].
• 0b is written to ICS_C1[IREFS].
• BDM mode is not active and ICS_C2[LP] bit is written to 1b.
In FLL bypassed external low-power mode, the ICSOUT clock is derived from the
external reference clock source and the FLL is disabled. The external reference clock
source is enabled.
12.4.1.7 Stop
The DCO frequency changes from the pre-stop value to its reset
value and the FLL need to re-acquire the lock before the
frequency is stable. Timing sensitive operations must wait for
the FLL acquisition time, t
Stop mode is entered whenever the MCU enters a STOP state.
NXP Semiconductors
NOTE
Acquire
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 12 Internal Clock Source (ICS)
, before executing.
199
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