Debug Comparator B Extension Register (Dbg_Cbx) - NXP Semiconductors MC9S08SU16 Reference Manual

28.3.10 Debug Comparator B Extension Register (DBG_CBX)

All the bits in this register reset to 0 in POR or non-end-run
reset. The bits are undefined in end-run reset. In the case of an
end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits
in this register do not change after reset.
Address: 18C0h base + 9h offset = 18C9h
Bit 7
Read
RWBEN
Write
Reset 0
Field
7 Read/Write Comparator B Enable Bit
RWBEN
The RWBEN bit controls whether read or write comparison is enabled for Comparator B. In full modes,
RWAEN and RWA are used to control comparison of R/W and RWBEN is ignored.
0 Read/Write is not used in comparison.
1 Read/Write is used in comparison.
6 Read/Write Comparator B Value Bit
RWB
The RWB bit controls whether read or write is used in compare for Comparator B. The RWB bit is not used
if RWBEN = 0.In full modes, RWAEN and RWA are used to control comparison of R/W and RWB is
ignored.
0 Write cycle will be matched.
1 Read cycle will be matched.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
NXP Semiconductors
NOTE
6 5
RWB
0 0
DBG_CBX field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0
0 0
Description
Chapter 28 Debug module (DBG)
2 1
0 0
0
0
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