System Port A Pin Multiplexing Control Register: High (Sim_Muxptah) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition
Field
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
MUXPTA0 Pin Mux Control
The corresponding pin is configured in the following pin muxing slot:
00 Alternative 0.
01 Alternative 1.
10 Alternative 2.
11 Alternative 3.
9.8.8 System Port A Pin Multiplexing Control Register: High
(SIM_MUXPTAH)
Many of the I/O pins are shared with on-chip peripheral functions. This register selects
the multiplexing pin functions from ALT0 to ALT3. Default is ALT0 function, When the
Pin Muxing mode is configured for analog pins, all the digital functions on that pin are
disabled, including the pullup/output/input.
The shared analog pin functions can work together if they're enabled separately because
they're directly connected to internal analog modules separately. They still work even
when pin Muxing mode is configured for digital pins.
KBI share with PTA on ALT3 and can be enable/disable by
KBI_PE register.
"RX and CLK_IN" function at different location must not be
selected at the same time to prevent signal override or
modulation.
Address: 1800h base + 7h offset = 1807h
Bit 7
Read
MUXPTA7
Write
Reset
0
112
SIM_MUXPTAL field descriptions (continued)
NOTE
6 5
MUXPTA6
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
MUXPTA5
0 0
2 1
MUXPTA4
0 0
NXP Semiconductors
0
0