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System interconnection
Module
Logic Low
Logic High
PWM_Sync
PWM0 or PWM1
PWM2 or PWM3
PWM4 or PWM5
PDB Channel0
PDB Channel1
FTM Channel0
FTM Channel1
GDU Phase A ACMP
GDU Phase B ACMP
GDU Phase C ACMP
CMP
Module
Package Pin
Package Pin
ADC0
ADC1
FTM Channel0
FTM Channel1
102
Table 9-2. XBAR module input signals from
(continued)
XBAR_INx
XBAR_IN2
XBAR_IN3
XBAR_IN4
XBAR_IN5
XBAR_IN6
XBAR_IN7
XBAR_IN8
XBAR_IN9
XBAR_IN10
XBAR_IN11
XBAR_IN12
XBAR_IN13
XBAR_IN14
XBAR_IN15
Table 9-3. XBAR module output
signals to
XBAR_OUTx
XBAR_OUT0
XBAR_OUT1
XBAR_OUT2
XBAR_OUT3
XBAR_OUT4
XBAR_OUT5
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Function
Logic Low
Logic High
XBAR_IN4
PWM0 or PWM1, selected by a
2-to-1 Mux
PWM2 or PWM3, selected by a
2-to-1 Mux
PWM4 or PWM5, selected by a
2-to-1 Mux
PDB_Ch0 Output
PDB_Ch1 Output
FTM_Ch0 Output
FTM_Ch1 Output
GDU phase A detection
comparator output
GDU phase B detection
comparator output
GDU phase C detection
comparator output
High speed analog comparator
output
Function
XB_OUT0
XB_OUT1
ADC0 hardware trigger input
ADC1 Hardware trigger input
FTM_Ch0 input capture or
output
FTM_Ch1 input capture or
output
NXP Semiconductors
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