Resets - NXP Semiconductors MC9S08SU16 Reference Manual

Resets

Field
5 PWM Compare Invert 5
CINV5
This bit controls the polarity of PWM compare output 5.
0 PWM output 5 is high when CNTR is less than VAL5
1 PWM output 5 is high when CNTR is greater than VAL5
4 PWM Compare Invert 4
CINV4
This bit controls the polarity of PWM compare output 4.
0 PWM output 4 is high when CNTR is less than VAL4
1 PWM output 4 is high when CNTR is greater than VAL4
3 PWM Compare Invert 3
CINV3
This bit controls the polarity of PWM compare output 3.
0 PWM output 3 is high when CNTR is less than VAL3
1 PWM output 3 is high when CNTR is greater than VAL3
2 PWM Compare Invert 2
CINV2
This bit controls the polarity of PWM compare output 2.
0 PWM output 2 is high when CNTR is less than VAL2
1 PWM output 2 is high when CNTR is greater than VAL2
1 PWM Compare Invert 1
CINV1
This bit controls the polarity of PWM compare output 1.
0 PWM output 1 is high when CNTR is less than VAL1
1 PWM output 1 is high when CNTR is greater than VAL1
0 PWM Compare Invert 0
CINV0
This bit controls the polarity of PWM compare output 0.
0 PWM output 0 is high when CNTR is less than VAL0
1 PWM output 0 is high when CNTR is greater than VAL0
26.5 Resets
All PWM registers are reset to their default values upon any system reset.
26.6 Clocks
The PWM operation clock runs at either system clock or 2 × system clock, which is
selected in the SIM module.
526
PWM_CINVH field descriptions (continued)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors