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Memory map and register definition
In output modes, writing to CnV latches the value into a buffer. The registers are updated
with the value of their write buffer according to
buffers.
This write coherency mechanism may be manually reset by writing to the CnSC register
whether BDM mode is active or not.
When BDM is active, the write coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active even if one or both
bytes of the channel value register are written while BDM is active. Any write to the CnV
registers bypasses the buffer latches and writes directly to the register while BDM is
active. The values written to the channel value registers while BDM is active are used in
output modes operation after normal execution resumes. Writes to the channel value
registers while BDM is active do not interfere with the partial completion of a coherency
sequence. After the write coherency mechanism has been fully exercised, the channel
value registers are updated using the buffered values while BDM was not active.
Address: 70h base + 6h offset + (3d × i), where i=0d to 1d
Bit
7
Read
Write
Reset
0
Field
VAL_H
Channel Value High Byte
Captured FTM counter value of the input capture function or the match value for the output modes
19.4.10 Channel Value Low (FTMx_CnVL)
See the description for the Channel Value High register.
Address: 70h base + 7h offset + (3d × i), where i=0d to 1d
Bit
7
Read
Write
Reset
0
Field
VAL_L
Channel Value Low Byte
Captured FTM counter value of the input capture function or the match value for the output modes
328
6
5
0
0
FTMx_CnVH field descriptions
6
5
0
0
FTMx_CnVL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Update of the registers with write
4
3
VAL_H
0
0
Description
4
3
VAL_L
0
0
Description
2
1
0
0
2
1
0
0
NXP Semiconductors
0
0
0
0
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