Resets - NXP Semiconductors MC9S08SU16 Reference Manual

the change of flow event. Because the system is configured for begin-trigger, the DBG
remains armed and does not break until the FIFO has been filled by subsequent change of
flow events.

28.5 Resets

The DBG module cannot cause an MCU reset.
There are two different ways this module will respond to reset depending upon the
conditions before the reset event. If the DBG module was setup for an end trace run with
DBG_C[DBGEN] = 1 and DBG_T[BEGIN] = 0, DBG_C[ARM], DBG_S[ARMF], and
DBG_C[BRKEN] are cleared but the reset function on most DBG control and status bits
is overridden so a host development system can read out the results of the trace run after
the MCU has been reset. In all other cases including POR, the DBG module controls are
initialized to start a begin trace run starting from when the reset vector is fetched. The
conditions for the default begin trace run are:
• DBG_CAX = 0x00, DBG_CAH=0xFF, DBG_CAL=0xFE so comparator A is set to
match when the 16-bit CPU address 0xFFFE appears during the reset vector fetch
• DBG_C = 0xC0 to enable and arm the DBG module
• DBG_T = 0x40 to select a force-type trigger, a BEGIN trigger, and A-only trigger
mode
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 28 Debug module (DBG)
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