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Reset overview
• The channels are in input capture mode
• The channels outputs are zero
• The channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0b00). See table
"Mode, Edge, and Level Selection"
The following figure shows the FTM behavior after the reset. At the reset (item 1), the
FTM counter is disabled (see table "FTM Clock Source Selection"), its value is updated
to zero and the pins are not controlled by FTM (table "Mode, Edge, and Level
Selection").
After the reset, the FTM should be configured (item 2). It is necessary to define the FTM
counter mode, the FTM counting limit (MODH:L registers value), the channels mode and
CnVH:L registers value according to the channels mode.
Because of this, you should write any value to CNTH or CNTL registers (item 3). This
write updates the FTM counter with the value of 0x0000 and the channels output with its
initial value (except for channels in output compare mode)
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is
important to highlight that the pins are controlled only by FTM when CLKS[1:0] bits are
different from zero (table "Mode, Edge, and Level Selection").
(1) FTM reset
FTM counter
XXXX
CLKS[1:0]
XX
channel (n) output
Note
– Channel (n) is in high-true EPWM mode with 0 < C(n)VH:L < MODH:L
– C(n)VH:L = 0x0005
Figure 19-17. FTM behavior after the reset when the channel (n) is in EPWM mode
The following figure shows an example when the channel (n) is in output compare mode
and the channel (n) output is toggled when there is a match. In the output compare mode,
the channel output is not updated to its initial value when there is a write to CNTH or
CNTL registers (item 3).
340
(3) write any value to
CNTH or CNTL registers
(4) write 0b01 to CLKS[1:0]
0x0000
00
(2) FTM configuration
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
(Input capture
mode)
(Counter
0x0001
0x0002
0x0003
0x0004
01
channel (n) pin is controlled by FTM
reset).
0x0007
0x0008
0x0005
0x0006
NXP Semiconductors
. . .
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