Limit0 Dac Control Register (Gdu_Limit0Daccr) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition
Field
0 Falling edge on COUT is not detected.
1 Falling edge on COUT occurs.
0 Analog Comparator Output
COUT
Reading the COUT bit returns the current value of the analog comparator output. This bit is reset to 0 and
reads as UCR1[INV] when the Analog Comparator module is disabled (UCR1[EN] = 0). Writing to this bit
has no effect.

25.6.21 LIMIT0 DAC Control Register (GDU_LIMIT0DACCR)

Address: 20h base + 1858h offset = 1878h
Bit 7
Read 0
Write
Reset
0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
VOSEL DAC Output Voltage Select
This field selects an output voltage from one of the 64 distinct levels.
DACO = (V
25.6.22 LIMIT1 CMP Control Register 0 (GDU_LIMIT1CR0)
Address: 20h base + 1859h offset = 1879h
Bit 7
Read 0
Write
Reset 0
Field
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
6–4 Filter Sample Count
FLTCNT
456
GDU_LIMIT0SCR field descriptions (continued)
6 5
0 0
GDU_LIMIT0DACCR field descriptions
/64) × (VOSEL[5:0] + 1), so the DACO range is from V
DDX
6 5
FLTCNT
0 0
GDU_LIMIT1CR0 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
VOSEL
0 0
Description
DDX
4 3
0 0
Description
2 1
0 0
/64 to V .
DDX
2 1
0
HYST
0 0
NXP Semiconductors
0
0
0
0