Table of Contents
Advertisement
Memory Map and Register Descriptions
26.4.8 PWM Output Control Register: High (PWM_OUTH)
Address: 40h base + 7h offset = 47h
Bit
7
Read
PADEN
Write
Reset
0
Field
7
Output Pad Enable
PADEN
The PWMn output pads can be enabled or disabled by setting the PAD_EN bit. The power-up default has
the pads disabled. This bit does not affect the functionality of the PWM, so the PWM module can be
energized with the output pads disabled. This enable is to power-up with a safe default value for the PWM
drivers.
0
Output pads disabled
1
Output pads enabled
6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
OUTCTL
Output Control Enables
These read/write bits enable software control of their corresponding PWM pin. When OUTCTLn is set, the
OUTn bit activates and deactivates the PWMn output or the CINVH register is used to select an alternate
control of the PWM outputs. A reset clears the OUTCTL bits.
0
Software control disabled (normal PWM operation)
1
Software control enabled
26.4.9 PWM Counter Register: Low (PWM_CNTRL)
This read-only register, together with CNTRH, displays the state of the 15-bit PWM
counter. Reading the CNTRL causes an internal hold register to be updated with the
CNTRH value. Reading the CNTRH reads this internal hold register. Always read the
lower byte before reading the upper byte in order to guarantee a coherent 15-bit value is
read.
Address: 40h base + 8h offset = 48h
Bit
7
Read
Write
Reset
0
514
6
5
0
0
0
PWM_OUTH field descriptions
6
5
0
0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4
3
OUTCTL
0
0
Description
4
3
CNTR7_0
0
0
2
1
0
0
2
1
0
0
NXP Semiconductors
0
0
0
0
Advertisement
Table of Contents
