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DBG Read Data Bus
Address Bus[16:0]
Write Data Bus
Read Data Bus
Read/Write
DBG Module Enable
mmu_ppage_access
core_cof[1:0]
MCU in BDM
MCU reset
Instr. Lastcycle
register
Bus Clk
subtract 2
Write Data Bus
Read Data Bus
Read/Write
28.2 Signal description
The DBG module contains no external signals.
28.3 Memory map and registers
This section provides a detailed description of all DBG registers accessible to the end
user.
NXP Semiconductors
Address/Data/Control Registers
c
o
n
t
r
Comparator A
o
l
Comparator B
1
Comparator C
Change of Flow Indicators
m
u
m
x
u
x
m
u
x
Figure 28-1. DBG block diagram
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 28 Debug module (DBG)
FIFO Data
control
match_A
match_B
match_C
event only
store
1
ppage_sel
m
8 deep
u
FIFO
x
1
addr[16:0]
Trigger
Break
Tag
Control
Logic
Force
Read DBGFL
Read DBGFH
Read DBGFX
FIFO Data
551
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