Analog Channel Inputs (Adx) - NXP Semiconductors MC9S08SU16 Reference Manual

ADC Control Registers

17.3.5 Analog Channel Inputs (ADx)

The ADC module supports up to 24 separate analog inputs. An input is selected for
conversion through the ADCH channel select bits.
17.4 ADC Control Registers
Absolute
address
(hex)
10 Status and Control Register 1 (ADC0_SC1)
11 Status and Control Register 2 (ADC0_SC2)
12 Status and Control Register 3 (ADC0_SC3)
13 Status and Control Register 4 (ADC0_SC4)
14 Conversion Result High Register (ADC0_RH)
15 Conversion Result Low Register (ADC0_RL)
16 Compare Value High Register (ADC0_CVH)
17 Compare Value Low Register (ADC0_CVL)
18 Status and Control Register 1 (ADC1_SC1)
19 Status and Control Register 2 (ADC1_SC2)
1A Status and Control Register 3 (ADC1_SC3)
1B Status and Control Register 4 (ADC1_SC4)
1C Conversion Result High Register (ADC1_RH)
1D Conversion Result Low Register (ADC1_RL)
1E Compare Value High Register (ADC1_CVH)
1F Compare Value Low Register (ADC1_CVL)
17.4.1 Status and Control Register 1 (ADCx_SC1)
This section describes the function of the ADC status and control register (ADC_SC1).
Writing ADC_SC1 aborts the current conversion and initiates a new conversion (if the
ADCH bits are equal to a value other than all 1s).
When FIFO is enabled, the analog input channel FIFO is written via ADCH. The analog
input channel queue must be written to ADCH continuously. The resulting FIFO follows
the order in which the analog input channel is written. The ADC will start conversion
when the input channel FIFO is fulfilled at the depth indicated by the
ADC_SC4[AFDEP]. Any write 0x1F to these bits will reset the FIFO and stop the
conversion if it is active.
262
ADC memory map
Register name
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access Reset value
(in bits)
8 R/W 1Fh
8 R/W 08h
8 R/W 00h
8 R/W 00h
8 R 00h
8 R 00h
8 R/W 00h
8 R/W 00h
8 R/W 1Fh
8 R/W 08h
8 R/W 00h
8 R/W 00h
8 R 00h
8 R 00h
8 R/W 00h
8 R/W 00h
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