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Initialization/application information
Clear IICIF
Tx
Last byte
transmitted?
N
RXAK=0?
Y
Y
End of
address cycle
(master Rx)?
N
Clear IICIF
Write next
byte to Data reg
Switch to
Rx mode
Generate stop
Dummy read
signal (MST=0)
from Data reg
Notes:
1. If general call or SIICAEN is enabled, check to determine if the received address is a general call address (0x00) or an SMBus
device default address. In either case, they must be handled by user software.
2. In receive mode, one bit time delay may be needed before the stop signal generation, to wait for the possible longest time
period (in worst case) of the 9th SCL cycle.
394
Y
Rx
Tx/Rx?
Y
Y
N
Last byte to be
read?
N
Read data from
Data reg
and soft CRC
Read data and
Soft CRC
Set TXAK to
proper value
Delay (Note 2)
Generate stop
signal (MST=0)
Set TXAK to
proper value
Clear IICIF
Figure 21-6. Typical I2C SMBus interrupt routine
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Entry of ISR
SLTF=1 or
SHTF2=1?
N
N
See typical I2C
FACK=1?
interrupt routine
flow chart
Y
N
Y
Master
mode?
Clear ARBL
N
IAAS=1?
Y
Y
(read)
SRW=1?
Read data from
Data reg
and soft CRC
Set TXAK to
proper value,
Clear IICIF
Delay (Note 2)
Set Tx mode
Write data
to Data reg
RTI
Y
Arbitration
lost?
N
Y
IAAS=1?
N
Address transfer
(see Note 1)
Tx/Rx?
Rx
N (write)
Tx
ACK from
receiver?
N
Read data from
Data reg
and soft CRC
Set TXAK to
Switch to
proper value,
Clear IICIF
Rx mode
Dummy read
from Data reg
NXP Semiconductors
Y
Clear IICIF
Transmit
next byte
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