NXP Semiconductors MC9S08PA4 Manuals

Manuals and User Guides for NXP Semiconductors MC9S08PA4. We have 1 NXP Semiconductors MC9S08PA4 manual available for free PDF download: Reference Manual

NXP Semiconductors MC9S08PA4 Reference Manual (401 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Table of Contents
3
Chapter 1 Device Overview

23
- Introduction
  23
- MCU Block Diagram
  24
- System Clock Distribution
  25
Chapter 2 Pins and Connections

29
Chapter 3 Power Management

37
- Introduction
  37
- Features
  37
  - Run Mode
    37
  - Wait Mode
    38
  - Stop3 Mode
    38
  - Active BDM Enabled in Stop3 Mode
    38
  - LVD Enabled in Stop Mode
    39
  - Power Modes Behaviors
    39
- Low Voltage Detect (LVD) System
  40
- Bandgap Reference
  42
- Power Management Control Bits and Registers
  42
  - System Power Management Status and Control 1 Register (PMC_SPMSC1)
    42
  - System Power Management Status and Control 2 Register (PMC_SPMSC2)
    44
Chapter 4 Memory Map

45
Chapter 5 Interrupt

97
Chapter 6 System Control

113
Chapter 7 Parallel Input/Output

131
Chapter 8 Clock Management

151
- Clock Module
  151
- Internal Clock Source (ICS)
  152
  - Function Description
    153
    
    Bus Frequency Divider
    154
    
    Low Power Bit Usage
    154
    
    Internal Reference Clock (ICSIRCLK)
    154
    
    Fixed Frequency Clock (ICSFFCLK)
    155
    
    BDC Clock
    156
  - Modes of Operation
    156
    
    FLL Engaged Internal (FEI)
    157
    
    FLL Engaged External (FEE)
    158
    
    FLL Bypassed Internal (FBI)
    158
    
    FLL Bypassed Internal Low Power (FBILP)
    158
    
    FLL Bypassed External (FBE)
    159
    
    FLL Bypassed External Low Power (FBELP)
    159
    
    Stop (STOP)
    160
  - FLL Lock and Clock Monitor
    161
    
    FLL Clock Lock
    161
    
    External Reference Clock Monitor
    161
- Initialization / Application Information
  161
  - Initializing FEI Mode
    162
  - Initializing FBI Mode
    162
  - Initializing FEE Mode
    162
  - Initializing FBE Mode
    163
  - External Oscillator (OSC)
    163
    
    Bypass Mode
    164
    
    Low-Power Configuration
    164
    
    High-Gain Configuration
    165
    
    Initializing External Oscillator for Peripherals
    165
- Khz Low-Power Oscillator (LPO)
  166
- Peripheral Clock Gating
  166
- ICS Control Registers
  166
- System Clock Gating Control Registers
  172
Chapter 9 Chip Configurations

177
- Introduction
  177
- Core Modules
  177
  - Central Processor Unit (CPU)
    177
  - Debug Module (DBG)
    177
- System Modules
  178
  - Watchdog (WDOG)
    178
- Clock Module
  178
- Memory
  180
  - Random-Access-Memory (RAM)
    180
  - Non-Volatile Memory (NVM)
    180
- Power Modules
  180
- Timers
  181
  - Flextimer Module (FTM)
    181
    
    FTM0 Interconnection
    182
    
    FTM1 Interconnection
    183
  - Real-Time Counter (RTC)
    183
- Communication Interfaces
  185
  - Serial Communications Interface (SCI)
    185
    
    SCI0 Infrared Functions
    186
- Analog
  187
  - Analog-To-Digital Converter (ADC)
    187
    
    ADC Channel Assignments
    188
    
    Alternate Clock
    190
    
    Hardware Trigger
    190
    
    Temperature Sensor
    190
  - Analog Comparator (ACMP)
    191
    
    ACMP Configuration Information
    193
    
    ACMP in Stop3 Mode
    193
    
    ACMP to FTM Configuration Information
    193
    
    ACMP for SCI0 RXD Filter
    193
- Human-Machine Interfaces HMI
  194
  - Keyboard Interrupts (KBI)
    194
Chapter 10 Central Processor Unit

197
- Introduction
  197
  - Features
    197
- Programmer's Model and CPU Registers
  198
  - Accumulator (A)
    198
  - Index Register (H:X)
    199
  - Stack Pointer (SP)
    199
  - Program Counter (PC)
    200
  - Condition Code Register (CCR)
    200
- Addressing Modes
  201
  - Inherent Addressing Mode (INH)
    202
  - Relative Addressing Mode (REL)
    202
  - Immediate Addressing Mode (IMM)
    202
  - Direct Addressing Mode (DIR)
    203
  - Extended Addressing Mode (EXT)
    203
  - Indexed Addressing Mode
    204
    
    Indexed, no Offset (IX)
    204
    
    Indexed, no Offset with Post Increment (IX+)
    204
    
    Indexed, 8-Bit Offset (IX1)
    204
    
    Indexed, 8-Bit Offset with Post Increment (IX1+)
    205
    
    Indexed, 16-Bit Offset (IX2)
    205
    
    SP-Relative, 8-Bit Offset (SP1)
    205
    
    SP-Relative, 16-Bit Offset (SP2)
    206
  - Memory to Memory Addressing Mode
    206
    
    Direct to Direct
    206
    
    Immediate to Direct
    206
    
    Indexed to Direct, Post Increment
    207
    
    Direct to Indexed, Post-Increment
    207
- Operation Modes
  207
  - Stop Mode
    207
  - Wait Mode
    208
  - Background Mode
    208
  - Security Mode
    209
- HCS08 V6 Opcodes
  211
- Special Operations
  211
  - Reset Sequence
    211
  - Interrupt Sequence
    211
- Instruction Set Summary
  212
Chapter 11 Keyboard Interrupts (KBI)

225
- Introduction
  225
  - Features
    225
  - Modes of Operation
    225
    
    KBI in Wait Mode
    225
    
    KBI in Stop Modes
    226
    
    KBI in Active Background Mode
    226
  - Block Diagram
    226
- External Signals Description
  227
- Register Definition
  227
- Memory Map and Registers
  227
- Functional Description
  229
  - Edge-Only Sensitivity
    230
  - Edge and Level Sensitivity
    230
  - KBI Pullup Resistor
    230
  - KBI Initialization
    231
Chapter 12

233
Flextimer Module (FTM)

233
- Introduction
  233
  - Flextimer Philosophy
    233
  - Features
    233
  - Modes of Operation
    234
  - Block Diagram
    234
- Signal Description
  235
  - EXTCLK - FTM External Clock
    236
  - Chn - FTM Channel (N) I/O Pin
    236
- Memory Map and Register Definition
  236
  - Module Memory Map
    236
  - Register Descriptions
    236
  - Status and Control (Ftmx_Sc)
    238
  - Counter High (Ftmx_Cnth)
    239
  - Counter Low (Ftmx_Cntl)
    240
  - Modulo High (Ftmx_Modh)
    240
  - Modulo Low (Ftmx_Modl)
    241
  - Channel Status and Control (Ftmx_Cnsc)
    241
  - Channel Value High (Ftmx_Cnvh)
    243
  - Channel Value Low (Ftmx_Cnvl)
    244
- Functional Description
  244
  - Clock Source
    245
    
    Counter Clock Source
    245
  - Prescaler
    246
  - Counter
    246
    
    Up Counting
    246
    
    Up-Down Counting
    247
    
    Free Running Counter
    248
    
    Counter Reset
    248
  - Input Capture Mode
    248
  - Output Compare Mode
    249
  - Edge-Aligned PWM (EPWM) Mode
    251
  - Center-Aligned PWM (CPWM) Mode
    252
  - Update of the Registers with Write Buffers
    254
    
    MODH:L Registers
    254
    
    Cnvh:l Registers
    255
  - BDM Mode
    255
- Reset Overview
  255
- FTM Interrupts
  257
  - Timer Overflow Interrupt
    257
  - Channel (N) Interrupt
    257
Chapter 13 Real-Time Counter (RTC)

259
- Introduction
  259
- Features
  259
  - Modes of Operation
    259
    
    Wait Mode
    260
    
    Stop Modes
    260
  - Block Diagram
    260
- Register Definition
  260
- Functional Description
  264
  - RTC Operation Example
    266
- Initialization/Application Information
  266
Chapter 14 Serial Communications Interface (SCI)

269
- Introduction
  269
  - Features
    269
  - Modes of Operation
    269
  - Block Diagram
    270
- SCI Signal Descriptions
  272
  - Detailed Signal Descriptions
    272
- Register Definition
  272
- Functional Description
  282
  - Baud Rate Generation
    283
  - Transmitter Functional Description
    283
    
    Send Break and Queued Idle
    284
  - Receiver Functional Description
    285
    
    Data Sampling Technique
    286
    
    Receiver Wake-Up Operation
    287
  - Interrupts and Status Flags
    288
  - Baud Rate Tolerance
    289
    
    Slow Data Tolerance
    289
    
    Fast Data Tolerance
    291
  - Additional SCI Functions
    292
    
    8- and 9-Bit Data Modes
    292
    
    Stop Mode Operation
    292
    
    Loop Mode
    293
    
    Single-Wire Operation
    293
Chapter 15 Analog-To-Digital Converter (ADC)

295
- Introduction
  295
  - Features
    295
  - Block Diagram
    296
- External Signal Description
  296
  - Analog Power (VDDA)
    297
  - Analog Ground (VSSA)
    297
  - Voltage Reference High (VREFH)
    297
  - Voltage Reference Low (VREFL)
    297
  - Analog Channel Inputs (Adx)
    297
- ADC Control Registers
  298
- Functional Description
  307
  - Clock Select and Divide Control
    308
  - Input Select and Pin Control
    308
  - Hardware Trigger
    309
  - Conversion Control
    309
    
    Initiating Conversions
    309
    
    Completing Conversions
    310
    
    Aborting Conversions
    310
    
    Power Control
    311
    
    Sample Time and Total Conversion Time
    311
  - Automatic Compare Function
    312
  - FIFO Operation
    313
  - MCU Wait Mode Operation
    317
  - MCU Stop3 Mode Operation
    317
    
    Stop3 Mode with ADACK Disabled
    317
    
    Stop3 Mode with ADACK Enabled
    317
- Initialization Information
  318
  - ADC Module Initialization Example
    318
    
    Initialization Sequence
    318
    
    Pseudo-Code Example
    319
  - ADC FIFO Module Initialization Example
    319
    
    Pseudo-Code Example
    320
- Application Information
  321
  - External Pins and Routing
    321
    
    Analog Supply Pins
    321
    
    Analog Reference Pins
    321
    
    Analog Input Pins
    322
  - Sources of Error
    323
    
    Sampling Error
    323
    
    Pin Leakage Error
    323
    
    Noise-Induced Errors
    323
    
    Code Width and Quantization Error
    325
    
    Linearity Errors
    325
    
    Code Jitter, Non-Monotonicity, and Missing Codes
    326
Chapter 16 Analog Comparator (ACMP)

327
- Introduction
  327
  - Features
    327
  - Modes of Operation
    328
    
    Operation in Wait Mode
    328
    
    Operation in Stop3 Mode
    328
    
    Operation in Debug Mode
    328
  - Block Diagram
    328
- External Signal Description
  329
- Memory Map and Register Definition
  329
- Functional Description
  332
- Setup and Operation of ACMP
  333
- Resets
  334
- Interrupts
  334
Chapter 17 Watchdog (WDOG)

335
- Introduction
  335
  - Features
    335
  - Block Diagram
    336
- Memory Map and Register Definition
  337
- Functional Description
  343
  - Watchdog Refresh Mechanism
    343
    
    Window Mode
    344
    
    Refreshing the Watchdog
    344
    
    Example Code: Refreshing the Watchdog
    345
  - Configuring the Watchdog
    345
    
    Reconfiguring the Watchdog
    346
    
    Unlocking the Watchdog
    346
    
    Example Code: Reconfiguring the Watchdog
    346
  - Clock Source
    347
  - Using Interrupts to Delay Resets
    348
  - Backup Reset
    348
  - Functionality in Debug and Low-Power Modes
    348
  - Fast Testing of the Watchdog
    349
    
    Testing each Byte of the Counter
    349
    
    Entering User Mode
    350
Chapter 18 Development Support

351
- Introduction
  351
  - Forcing Active Background
    351
  - Features
    351
- Background Debug Controller (BDC)
  352
  - BKGD Pin Description
    353
  - Communication Details
    354
  - BDC Commands
    356
  - BDC Hardware Breakpoint
    359
- On-Chip Debug System (DBG)
  359
  - Comparators a and B
    360
  - Bus Capture Information and FIFO Operation
    360
  - Change-Of-Flow Information
    361
  - Tag Vs. Force Breakpoints and Triggers
    362
  - Trigger Modes
    363
  - Hardware Breakpoints
    364
- Memory Map and Register Description
  365
Chapter 19 Debug Module (DBG)

371
- Introduction
  371
  - Features
    371
  - Modes of Operation
    372
  - Block Diagram
    372
- Signal Description
  373
- Memory Map and Registers
  373
- Functional Description
  388
  - Comparator
    388
    
    RWA and RWAEN in Full Modes
    388
    
    Comparator C in Loop1 Capture Mode
    388
  - Breakpoints
    389
    
    Hardware Breakpoints
    389
  - Trigger Selection
    390
  - Trigger Break Control (TBC)
    390
    
    Begin- and End-Trigger
    391
    
    Arming the DBG Module
    391
    
    Trigger Modes
    392
  - Fifo
    395
    
    Storing Data in FIFO
    395
    
    Storing with Begin-Trigger
    395
    
    Storing with End-Trigger
    395
    
    Reading Data from FIFO
    395
  - Interrupt Priority
    396
- Resets
  397

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NXP Semiconductors MC9S08PA4 Manuals

NXP Semiconductors MC9S08PA4 Reference Manual (401 pages)

Table of Contents

Chapter 1 Device Overview

Chapter 2 Pins and Connections

Chapter 3 Power Management

Chapter 4 Memory Map

Chapter 5 Interrupt

Chapter 6 System Control

Chapter 7 Parallel Input/Output

Chapter 8 Clock Management

Chapter 9 Chip Configurations

Chapter 10 Central Processor Unit

Chapter 11 Keyboard Interrupts (KBI)

Chapter 12

Flextimer Module (FTM)

Chapter 13 Real-Time Counter (RTC)

Chapter 14 Serial Communications Interface (SCI)

Chapter 15 Analog-To-Digital Converter (ADC)

Chapter 16 Analog Comparator (ACMP)

Chapter 17 Watchdog (WDOG)

Chapter 18 Development Support

Chapter 19 Debug Module (DBG)

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