Interrupt Priority Level Register; Interrupt Priority Level Comparator Set; Interrupt Priority Mask Update And Restore Mechanism - NXP Semiconductors MC9S08SU16 Reference Manual

• The interrupt priority level registers
• The interrupt priority level comparator set
• The interrupt mask register update and restore mechanism

4.1.2.1 Interrupt priority level register

This set of registers is associated with the interrupt sources to the HCS08 CPU. Each
interrupt priority level is a 2-bit value such that a user can program the interrupt priority
level of each source to priority 0, 1, 2, or 3. Level 3 has the highest priority while level 0
has the lowest. Software can read or write to these registers at any time. The interrupt
priority level comparator set, interrupt mask register update, and restore mechanism use
this information.

4.1.2.2 Interrupt priority level comparator set

When the module is enabled, an active interrupt request forces a comparison between the
corresponding ILR and the 2-bit interrupt mask IPM[1:0]. In stop mode, the IPM[1:0] is
substituted by value 00b. If the ILR value is greater than or equal to the value of the
interrupt priority mask (IPM bits in IPCSC), the corresponding interrupt out (INTOUT)
signal will be asserted and signals an interrupt request to the HCS08 CPU.
When the module is disabled, the interrupt request signal from the source is directly
passed to the CPU.
The interrupt priority level programmed in the interrupt priority register will not affect
the inherent interrupt priority arbitration as defined by the HCS08 CPU because the IPC
is an external module. Therefore, if two (or more) interrupts are present in the HCS08
CPU at the same time, the inherent priority in HCS08 CPU will perform arbitration by
the inherent interrupt priority.

4.1.2.3 Interrupt priority mask update and restore mechanism

The interrupt priority mask (IPM) is two bits located in the least significant end of IPCSC
register. These two bits control which interrupt is allowed to be presented to the HCS08
CPU. During vector fetch, the interrupt priority mask is updated automatically with the
value of the ILR corresponding to that interrupt source. The original value of the IPM
will be saved onto IPMPS for restoration after the interrupt service routine completes
execution. When the interrupt service routine completes execution, the user restore the
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 4 Interrupt
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