Table of Contents
Advertisement
host-to-target transmissions to speed up rising edges. Because the target does not drive
the BKGD pin during the host-to-target transmission period, there is no need to treat the
line as an open-drain signal during this period.
B D C C L O C K
(T A R G E T M C U )
H O S T
T R A N S M IT 1
H O S T
T R A N S M IT 0
S Y N C H R O N IZ A T IO N
U N C E R T A IN T Y
P E R C E IV E D S T A R T
O F B IT T IM E
The next figure shows the host receiving a logic 1 from the target HCS08 MCU. Because
the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-
generated falling edge on BKGD to the perceived start of the bit time in the target MCU.
The host holds the BKGD pin low long enough for the target to recognize it (at least two
target BDC cycles). The host must release the low drive before the target MCU drives a
brief active-high speedup pulse seven cycles after the perceived start of the bit time. The
host should sample the bit level about 10 cycles after it started the bit time.
B D C C L O C K
(T A R G E T M C U )
H O S T D R IV E
T O B K G D P IN
T A R G E T M C U
S P E E D U P P U L S E
P E R C E IV E D S T A R T
O F B IT T IM E
B K G D P IN
Figure 27-3. BDC target-to-host serial bit timing (logic 1)
NXP Semiconductors
1 0 C Y C L E S
T A R G E T S E N S E S B IT L E V E L
Figure 27-2. BDC host-to-target serial bit timing
H IG H -IM P E D A N C E
R -C R IS E
1 0 C Y C L E S
1 0 C Y C L E S
H O S T S A M P L E S B K G D P IN
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 27 Development support
E A R L IE S T S T A R T
O F N E X T B IT
H IG H -IM P E D A N C E
H IG H -IM P E D A N C E
E A R L IE S T S T A R T
O F N E X T B IT
533
Advertisement
Table of Contents
