Master Microwire Serial Transfers - Altera cyclone V Technical Reference

19-26

Master Microwire Serial Transfers

6. The shift control logic stops the transfer when the transmit FIFO buffer is empty. If the transfer mode is
receive only (
have been received. When the transfer is done, the
7. If the transfer mode is not transmit only (
empty
8. Disable the SPI master by writing 0 to
Master Microwire Serial Transfers
Figure 19-16: Microwire Serial
Altera Corporation
= 2), the shift control logic stops the transfer when the specified number of frames
TMOD
Idle
Disable SPI
Configure Master by Writing
CTRLR0, CTRLR1, BAUDR,
TXFTLR, RXFTLR, MWCR,
IMR & SER
Enable SPI
Write Control &
Data to Tx FIFO
Transfer
in Progress
Interrupt?
no
Busy?
no
Read Rx
FIFO
status is reset to 0.
BUSY
is not equal to 1), read the receive FIFO buffer until it is
TMOD
.
SSIENR
If the master receives data, the user only
needs to write control frames into the TX
FIFO. Transfer begins when the first control
word is present in the transmit FIFO and a
slave is enabled.
yes
Interrupt Service
Routine
If the transmit FIFO makes the request
and all data has not been sent, write
data to the transmit FIFO.
yes
If the receive FIFO makes the request,
read data from the receive FIFO.
MWCR[1] = 1
SPI Controller
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cv_5v4
2016.10.28