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16.4.3.3 High Speed Run (HSRUN) mode
In HSRUN mode, the on-chip voltage regulator remains in a run regulation state, but with
a slightly elevated voltage output. In this state, the MCU is able to operate at a faster
frequency compared to normal RUN mode. See Power Management chapter for
maximum allowable frequencies.
While in this mode, the following restrictions must be adhered to:
• The maximum allowable change in frequency of the system, bus, flash or core clocks
is restricted to x2.
• Before exiting HSRUN mode, clock frequencies should be reduced back down to
those acceptable in RUN mode.
• Stop mode entry is not supported from HSRUN.
• Modifications to clock gating control bits are prohibited.
• Flash programming/erasing is not allowed.
To enter HSRUN mode, set PMPORT[AHSRUN]=HSRUN and set
PMCTRL[RUNM]=HSRUN. Before increasing clock frequencies, the PMSTAT register
should be polled to determine when the system has completed entry into HSRUN mode.
To reenter normal RUN mode, clear RUNM. Any reset will also clear RUNM and cause
the system to exit to normal RUN mode after the MCU exits its reset flow.
16.4.4 Wait modes
This device contains two different wait modes which are listed here.
• Wait
• Very-Low Power Wait (VLPW)
16.4.4.1 WAIT mode
WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit
modes while SLEEDEEP is cleared. The ARM CPU enters a low-power state in which it
is not clocked, but peripherals continue to be clocked provided they are enabled. Clock
gating to the peripheral is enabled via the SIM module.
When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in
RUN mode, beginning with the stacking operations leading to the interrupt service
routine.
A system reset will cause an exit from WAIT mode, returning the device to normal RUN
mode.
Freescale Semiconductor, Inc.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 16 System Mode Controller (SMC)
279
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