Debug Resets - NXP Semiconductors freescale KV4 Series Reference Manual

Debug Resets

Table 9-5. MDM-AP Status register assignments (continued)
Bit Name
11 – 15 Reserved for future use
16 Core Halted
17 Core SLEEPDEEP
18 Core SLEEPING
19 – 31 Reserved for future use
9.5 Debug Resets
The debug system receives the following sources of reset:
• JTAG_TRST_b from an external signal. This signal is optional and may not be
available in all packages.
• Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the
TCLK domain that allows the debugger to reset the debug logic.
• TRST asserted via the cJTAG escape command.
• System POR reset
Conversely the debug system is capable of generating system reset using the following
mechanism:
• A system reset in the DAP control register which allows the debugger to hold the
system in reset.
• SYSRESETREQ bit in the NVIC application interrupt and reset control register
• A system reset in the DAP control register which allows the debugger to hold the
Core in reset.
9.6 AHB-AP
AHB-AP provides the debugger access to all memory and registers in the system,
including processor registers through the NVIC. System access is independent of the
processor status. AHB-AP does not do back-to-back transactions on the bus, so all
transactions are non-sequential. AHB-AP can perform unaligned and bit-band
transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP
124
This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit
bit is held until the debugger has had a chance to recognize that a VLLS
mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status
Acknowledge bit in MDM AP Control register.
Always read 0.
Indicates the Core has entered debug halt mode
Indicates the Core has entered a low power mode
SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode.
SLEEPING==0 and SLEEPDEEP==1 indicates stop or VLPS mode.
Always read 0.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Description
Freescale Semiconductor, Inc.