Table of Contents
Advertisement
Section 20 Power-Down State
20.4
Software Standby Mode
20.4.1
Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules
are reset and halted. As long as the specified voltage is supplied, however, CPU register contents
and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface* are also
held. When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0
before setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their
previous states.
20.4.2
Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ
IRQ
pin, or by input at the RES or STBY pin.
2
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ
0
CPU.
Exit by RES
RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
RES
RES
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY
STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
STBY
STBY
Rev. 4.00 Jan 26, 2006 page 684 of 938
REJ09B0276-0400
, IRQ
0
, IRQ
, and IRQ
are cleared to 0, or if these interrupts are masked in the
1
2
, or IRQ
interrupt request signal is received, the
1
2
, IRQ
, or
0
1
Advertisement
Table of Contents
