Renesas H8/3067 Series User Manual page 370

Section 9 16-Bit Timer
Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables
the interrupt requested by the IMFB1 flag when IMFB1 is set to 1.
Bit 5
IMIEB1 Description
0 IMIB1 interrupt requested by IMFB1 flag is disabled
1 IMIB1 interrupt requested by IMFB1 flag is enabled
Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables
the interrupt requested by the IMFB0 flag when IMFB0 is set to 1.
Bit 4
IMIEB0 Description
0 IMIB0 interrupt requested by IMFB0 flag is disabled
1 IMIB0 interrupt requested by IMFB0 flag is enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2
compare match or input capture events.
Bit 2
IMFB2 Description
0 [Clearing condition]
Read IMFB2 when IMFB2 =1, then write 0 in IMFB2.
1 [Setting conditions]
TCNT2 = GRB2 when GRB2 functions as an output compare register.
TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as
an input capture register.
Rev. 4.00 Jan 26, 2006 page 346 of 938
REJ09B0276-0400
(Initial value)
(Initial value)
(Initial value)