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Section 8 I/O Ports
8.8.2
Register Description
Table 8.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction
register.
Table 8.12 Port 7 Data Register
Address*
Name
H'FFFD6
Port 7 data register
Note: * Lower 20 bits of the address in advanced mode.
Port 7 Data Register (P7DR)
Bit
7
P7
Initial value
Read/Write
R
Note: *
Determined by pins P7 to P7 .
When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.
Rev. 4.00 Jan 26, 2006 page 294 of 938
REJ09B0276-0400
6
5
P7
P7
7
6
5
*
*
*
R
R
7
0
Abbreviation
R/W
P7DR
R
4
3
2
P7
P7
P7
4
3
*
*
R
R
R
Initial Value
Undetermined
1
0
P7
P7
2
1
0
*
*
*
R
R
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