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Section 11 Programmable Timing Pattern Controller (TPC)
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the TPC.
16-bit timer compare match signals
TP
15
TP
Pulse output
14
TP
pins, group 3
13
TP
12
TP
11
TP
Pulse output
10
pins, group 2
TP
9
TP
8
TP
7
Pulse output
TP
6
pins, group 1
TP
5
TP
4
TP
3
Pulse output
TP
2
pins, group 0
TP
1
TP
0
Legend
TPMR:
TPC output mode register
TPCR:
TPC output control register
NDERB:
Next data enable register B
NDERA:
Next data enable register A
PBDDR:
Port B data direction register
PADDR:
Port A data direction register
NDRB:
Next data register B
NDRA:
Next data register A
PBDR:
Port B data register
PADR:
Port A data register
Rev. 4.00 Jan 26, 2006 page 436 of 938
REJ09B0276-0400
Control logic
PBDR
PADR
Figure 11.1 TPC Block Diagram
PADDR
PBDDR
NDERA
NDERB
TPMR
TPCR
NDRB
NDRA
Internal
data bus
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