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7.4.2
I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified
in MAR to the address specified in IOAR otherwise.
Table 7.6 indicates the register functions in I/O mode.
Table 7.6
Register Functions in I/O Mode
Register
23
MAR
23
7
All 1s
IOAR
15
ETCR
Legend
MAR:
Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Function
Activated by
SCI 0 Receive-
Data-Full
Interrupt or by
A/D Converter
Conversion-
Other
End Interrupt
Activation
0
Destination
Source
address
address
register
register
0
Source
Destination
address
address
register
register
0
Transfer counter
Section 7 DMA Controller
Initial Setting
Destination or
source start
address
Source or
destination
address
Number of
transfers
Rev. 4.00 Jan 26, 2006 page 231 of 938
Operation
Incremented or
decremented
once per
transfer
Held fixed
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
REJ09B0276-0400
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