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Section 6 Bus Controller
Address bus
Read access
Write access
Note: n = 7 to 0
Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
Rev. 4.00 Jan 26, 2006 page 160 of 938
REJ09B0276-0400
T
φ
CS
n
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
D
to D
15
8
D
to D
7
0
(Word Access)
Bus cycle
T
1
2
External address in area n
Valid
Valid
T
3
Valid
Valid
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