Idle Mode - Renesas H8/3067 Series User Manual

Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,
conversion-end interrupts from the A/D converter, and external request signals.
For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).
Figure 7.3 shows a sample setup procedure for I/O mode.
I/O mode setup
Set source and
destination addresses
Set transfer count
Read DTCR
Set DTCR
I/O mode
7.4.3

Idle Mode

Idle mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in idle mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the
address specified in MAR to the address specified in IOAR otherwise.
1.
1
2.
3.
4.
2
3
4
Figure 7.3 I/O Mode Setup Procedure (Example)
Set the source and destination addresses
in MAR and IOAR. The transfer direction is
determined automatically from the activation
source.
Set the transfer count in ETCR.
Read DTCR while the DTE bit is cleared to 0.
Set the DTCR bits as follows.
•
Select the DMAC activation source with bits
DTS2 to DTS0.
•
Set or clear the DTIE bit to enable or disable
the CPU interrupt at the end of the transfer.
•
Clear the RPE bit to 0 to select I/O mode.
•
Select MAR increment or decrement with the
DTID bit.
•
Select byte size or word size with the DTSZ bit.
•
Set the DTE bit to 1 to enable the transfer.
Rev. 4.00 Jan 26, 2006 page 233 of 938
Section 7 DMA Controller
REJ09B0276-0400