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φ
RTCNT
RTCOR
Refresh request signal
and CMF bit setting signal
φ
Address bus*
CS
(RAS)
n
PB
/PB
4
5
(UCAS/LCAS)
RD(WE)
RFSH
AS
Note: * In address update mode 1, the area 2 start address is output.
In address update mode 2, the address in the preceding bus cycle is retained.
Figure 6.28 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)
N
Figure 6.27 Compare Match Timing
T
Rp
Area 2 start address
High
High level
N
T
T
R1
R2
Rev. 4.00 Jan 26, 2006 page 181 of 938
Section 6 Bus Controller
H'00
REJ09B0276-0400
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