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Section 2 CPU
φ
Address bus
AS
,
RD HWR LWR
,
,
D
to D
15
0
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4
Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.
Rev. 4.00 Jan 26, 2006 page 62 of 938
REJ09B0276-0400
T
1
High
High impedance
T
T
2
Address
3
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