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φ
Address bus
Data bus
AS
RD
HWR, LWR
BREQ
BACK
Figure 6.48 Example of External Bus Master Operation
In the event of contention with a bus request from an external bus master when a transition is
made to software standby mode, the BACK and strobe states may be indeterminate after the
transition to software standby mode (see figure 6.36).
When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before
executing the SLEEP instruction.
CPU cycles
T
T
T
0
1
2
Address
High
Minimum 3 cycles
(1)
(2)
Section 6 Bus Controller
External bus released
High-impedance
High-impedance
High-impedance
High-impedance
High-impedance
(3)
(4)
(5)
Rev. 4.00 Jan 26, 2006 page 205 of 938
CPU cycles
(6)
REJ09B0276-0400
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