Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 Details should always be checked by referring to the relevant text. H8/3644 Group, H8/3644R Group H8/3644 F-ZTAT , H8/3643 F-ZTAT H8/3642A F-ZTAT Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series H8/3644 HD6473644 H8/3644R HD6473644R HD6433644 HD6433644R...
Page 4 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 5 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 6 Rev. 6.00 Sep 12, 2006 page iv of xx...
Page 7 Preface The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3644 Group has a system-on-a-chip architecture that includes such peripheral functions as a D/A converter, five timers, a 14-bit PWM, a two-channel serial communication interface, and an A/D converter.
Page 8 Rev. 6.00 Sep 12, 2006 page vi of xx...
Page 9 Revision (See Manual for Details) — • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8/3644 Series → (After) H8/3644 Group (Before) H8/3644R Series → (After) H8/3644R Group 3.3.2 Interrupt Control...
Page 10 Item Page Revision (See Manual for Details) 10.2.2 Register Description amended Descriptions SCSR1 is an 8-bit register indicating operation status and Serial Control/Status error status. Register 1 (SCSR1) 10.3.1 Overview Figure amended Figure 10.6 SCI3 Internal clock (φ/64, φ/16, φ/4, φ) External Block Diagram clock...
Page 11 Item Page Revision (See Manual for Details) 13.2.4 DC Table amended Characteristics Values Applicable (HD6433644, Item Symbol Pins Typ Max Unit Test Condition Notes HD6433643,  Active Active (high- 1, 2 OPE1 mode speed) mode HD6433642, current = 5 V, HD6433641, dissipation = 10 MHz...
Page 12 Item Page Revision (See Manual for Details) A.1 Instructions Table amended Table A.1 Instruction Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C SP–2 → SP PUSH Rs — — 0 — 6 Rs16 → @SP Rd8+#xx:8 →...
Page 13: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Internal Block Diagram..................... Pin Arrangement and Functions ..................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ....................... 10 Section 2 CPU ........................15 Overview........................... 15 2.1.1 Features........................ 15 2.1.2 Address Space...................... 16 2.1.3 Register Configuration ..................16 Register Descriptions ......................
Page 14 2.7.4 Exception-Handling State ..................48 Memory Map........................49 Application Notes ......................50 2.9.1 Notes on Data Access ..................50 2.9.2 Notes on Bit Manipulation ................... 52 2.9.3 Notes on Use of the EEPMOV Instruction ............58 Section 3 Exception Handling ..................
Page 15 5.3.1 Transition to Standby Mode................. 95 5.3.2 Clearing Standby Mode..................95 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared ........96 Watch Mode........................96 5.4.1 Transition to Watch Mode ................... 96 5.4.2 Clearing Watch Mode ..................97 5.4.3 Oscillator Settling Time after Watch Mode Is Cleared ........97 Subsleep Mode........................
Page 16 On-Board Programming Modes ..................120 6.6.1 Boot Mode ......................120 6.6.2 User Program Mode..................... 125 Programming and Erasing Flash Memory................. 127 6.7.1 Program Mode ..................... 127 6.7.2 Program-Verify Mode..................128 6.7.3 Programming Flowchart and Sample Program............. 129 6.7.4 Erase Mode ......................132 6.7.5 Erase-Verify Mode....................
Page 17 8.4.5 MOS Input Pull-Up....................185 Port 5..........................186 8.5.1 Overview......................186 8.5.2 Register Configuration and Description............... 186 8.5.3 Pin Functions ....................... 188 8.5.4 Pin States......................189 8.5.5 MOS Input Pull-Up....................189 Port 6..........................190 8.6.1 Overview......................190 8.6.2 Register Configuration and Description............... 190 8.6.3 Pin Functions .......................
Page 18 9.3.1 Overview......................209 9.3.2 Register Descriptions ................... 211 9.3.3 Timer Operation....................213 9.3.4 Timer B1 Operation States................... 214 Timer V..........................215 9.4.1 Overview......................215 9.4.2 Register Descriptions ................... 218 9.4.3 Timer Operation....................224 9.4.4 Timer V Operation Modes ................... 229 9.4.5 Interrupt Sources....................
Page 19 10.3.6 Multiprocessor Communication Function ............329 10.3.7 Interrupts......................336 10.3.8 Application Notes ....................337 Section 11 14-Bit PWM ..................... 341 11.1 Overview........................... 341 11.1.1 Features........................ 341 11.1.2 Block Diagram ..................... 341 11.1.3 Pin Configuration....................342 11.1.4 Register Configuration ..................342 11.2 Register Descriptions ......................
Page 20 13.2.5 AC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) ......................376 13.2.6 A/D Converter Characteristics ................381 13.3 Electrical Characteristics (ZTAT and R of the Mask ROM Version) ....... 382 13.3.1 Power Supply Voltage and Operating Range ............382 13.3.2 DC Characteristics (HD6473644R) ..............385 13.3.3 AC Characteristics (HD6473644R) ..............
Page 21 Appendix E Product Code Lineup .................. 522 Appendix F Package Dimensions ................... 524 Rev. 6.00 Sep 12, 2006 page xix of xx...
Page 22 Rev. 6.00 Sep 12, 2006 page xx of xx...
Page 23: Section 1 Overview
Table 1 summarizes the features of the H8/3644 Group. Notes: 1. ZTAT is a trademark of Renesas Technology Corp. 2. F-ZTAT is a trademark of Renesas Technology Corp. Rev. 6.00 Sep 12, 2006 page 1 of 526...
Page 24 Section 1 Overview Table 1.1 Features Item Description High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed  Max. operation speed: 5 MHz (mask ROM and ZTAT versions) 8 MHz (Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version) ...
Page 25 Section 1 Overview Item Description Power-down Seven power-down modes modes • Sleep (high-speed) mode • Sleep (medium-speed) mode • Standby mode • Watch mode • Subsleep mode • Subactive mode • Active (medium-speed) mode Memory Large on-chip memory • H8/3644: 32-kbyte ROM, 1-kbyte RAM •...
Page 26 Section 1 Overview Item Description Timers • Timer X: 16-bit timer  Count-up timer with selection of three internal clock signals or event input from external pin  Output compare (2 output pins)  Input capture (4 input pins) • Watchdog timer ...
Page 27 Section 1 Overview Item Description Product lineup Product Code Mask ROM ZTAT™ F-ZTAT™ Version Version Version Package ROM/RAM Size HD6433644H HD6473644H HD64F3644H 64-pin QFP ROM: 32 kbytes HD6433644RH HD6473644RH (FP-64A) RAM: 1 kbyte HD6433644P HD6473644P HD64F3644P 64-pin SDIP HD6433644RP HD6473644RP (DP-64S) HD6433644W HD6473644W...
Page 28: Internal Block Diagram
Section 1 Overview Internal Block Diagram Figure 1.1 shows a block diagram of the H8/3644 Group. H8/300L Data bus (lower) /FTID /FTIC /FTIB /FTIA /FTOB /FTOA /TMOW /FTCI /PWM /IRQ /IRQ /IRQ /TRGV /SCK /TMOV Timer A SCI1 /RXD /TMCIV /TXD /TMRIV Timer B1...
Page 29: Pin Arrangement And Functions
Section 1 Overview Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3644 Group pin arrangement is shown in figures 1.2 (FP-64A), 1.3 (DP-64S), and 1.4 (TFP-80C). /TXD /INT /INT /TMIB /INT /ADTRG /INT /SCK /INT /TMOW /PWM /INT /IRQ /INT /IRQ /INT /IRQ...
Page 30 Section 1 Overview /IRQ /TRGV /IRQ /IRQ /PWM /TMOW /SCK /TXD /RXD /SCK TEST /FTID /FTIC /FTIB /FTIA /FTOB /FTOA /FTCI /TMOV /TMCIV /TMRIV /INT /INT /TMIB /INT /ADTRG /INT /INT /INT /INT /INT Note: * There is no P9 function in the flash memory version.
Page 31 Section 1 Overview /TXD /INT /INT /TMIB /INT /ADTRG /SCK /INT /TMOW /INT /PWM /INT /IRQ /INT /IRQ /INT /IRQ /TRGV Note: * There is no P9 function in the flash memory version. Figure 1.4 Pin Arrangement (TFP-80C: Top View) Rev.
Page 32: Pin Functions
Section 1 Overview 1.3.2 Pin Functions Table 1.2 outlines the pin functions of the H8/3644 Group. Table 1.2 Pin Functions Pin No. Type Symbol FP-64A DP-64S TFP-80C I/O Name and Functions Power Input Power supply: All V pins source pins should be connected to the user system V 8, 11...
Page 33 Section 1 Overview Pin No. Type Symbol FP-64A DP-64S TFP-80C I/O Name and Functions Interrupt Input IRQ interrupt request 0 to 3: pins These are input pins for edge- sensitive external interrupts, with a selection of rising or falling edge 32 to 25 40 to 33 38 to 31 Input INT interrupt request 0 to 7:...
Page 34 Section 1 Overview Pin No. Type Symbol FP-64A DP-64S TFP-80C I/O Name and Functions Timer pins FTIA Input Timer X input capture A input: This is an input pin for timer X input capture A FTIB Input Timer X input capture B input: This is an input pin for timer X input capture B FTIC...
Page 35 Section 1 Overview Pin No. Type Symbol FP-64A DP-64S TFP-80C I/O Name and Functions I/O ports 38 to 34 46 to 42 47 to 43 Port 7: This is a 5-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7) 46 to 39 54 to 47 57 to 54, Port 8: This is an 8-bit I/O port.
Page 36 Section 1 Overview Pin No. Type Symbol FP-64A DP-64S TFP-80C I/O Name and Functions Flash Input On-board-programmable flash memory memory power supply: Connected to the flash memory programming power supply (+12 V). When the flash memory is not being programmed, connect to the user system V In versions other than the on-chip flash memory version, this pin is...
Page 37: Section 2 Cpu
Section 2 CPU Section 2 CPU Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 38: Address Space
Section 2 CPU • Low-power operation modes SLEEP instruction for transfer to low-power operation 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU.
Page 39 Section 2 CPU General registers (Rn) SP: Stack pointer (SP) Control registers (CR) PC: Program counter 3 2 1 0 I U H U N Z V C CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit...
Page 40: Register Descriptions
Section 2 CPU Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
Page 41 Section 2 CPU Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions).
Page 42: Initial Register Values
Section 2 CPU Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 2.2.3 Initial Register Values In reset exception handling, the program counter (PC) is initialized by a vector address (H'0000) load, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
Page 43: Data Formats In General Registers
Section 2 CPU 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. Data Format 1-bit data don’t care 1-bit data don’t care Byte data don’t care Byte data...
Page 44: Memory Data Formats
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. When word data beginning at an odd address is accessed, the least significant bit is regarded as 0, and the word data beginning at the preceding address is accessed.
Page 45: Addressing Modes
Section 2 CPU Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment...
Page 46 Section 2 CPU  Register indirect with pre-decrement@–Rn The @–Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value.
Page 47: Effective Address Calculation
Section 2 CPU 2.4.2 Effective Address Calculation Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8).
Page 48 Section 2 CPU Table 2.2 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Register indirect, Rn Operand is contents of registers indicated by rm/rn Register indirect, @Rn Contents (16 bits) of register indicated by rm Register indirect with displacement, @(d:16, Rn) Contents (16 bits) of...
Page 49 Section 2 CPU Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Absolute address @aa:8 H'FF @aa:16 Immediate Operand is 1- or 2-byte #xx:8 immediate data #xx:16 Program-counter relative PC contents @(d:8, PC) Sign disp extension disp Rev.
Page 50 Section 2 CPU Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Memory indirect, @@aa:8 H'00 Memory contents (16 bits) Legend: rm, rn: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address Rev. 6.00 Sep 12, 2006 page 28 of 526 REJ09B0326-0600...
Page 51: Instruction Set
Section 2 CPU Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Number MOV, PUSH * , POP * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations...
Page 52 Section 2 CPU Notation General register (destination) General register (source) General register (EAd), <Ead> Destination operand (EAs), <Eas> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 53: Data Transfer Instructions
Section 2 CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 54 Section 2 CPU Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@–Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @–SP Legend: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes Rev.
Page 55: Arithmetic Operations
Section 2 CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Size * Instruction Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register.
Page 56: Logic Operations
Section 2 CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 57 Section 2 CPU Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR...
Page 58: Bit Manipulations
Section 2 CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 59 Section 2 CPU Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 60 Section 2 CPU BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.:...
Page 61 Section 2 CPU BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Legend: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont)
Page 62: Branching Instructions
Section 2 CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Size * Instruction Function  Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition...
Page 63 Section 2 CPU disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Legend: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes Rev. 6.00 Sep 12, 2006 page 41 of 526 REJ09B0326-0600...
Page 64: System Control Instructions
Section 2 CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Size * Instruction Function  Returns from an exception-handling routine  SLEEP Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Page 65: Block Data Transfer Instruction
Section 2 CPU RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Legend: Operation field Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size...
Page 66: Basic Operational Timing
Section 2 CPU Legend: Operation field Figure 2.10 Block Data Transfer Instruction Code Basic Operational Timing CPU operation is synchronized by a system clock (φ) or a subclock (φ ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ the next rising edge is called one state.
Page 67: Access To On-Chip Peripheral Modules
Section 2 CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 68: Cpu States
Section 2 CPU Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in the case of three-state access to an on-chip peripheral module. Bus cycle state state state φ or φ Internal Address address bus Internal read signal Internal Read data data bus...
Page 69 Section 2 CPU CPU state Reset state The CPU is initialized Program Active execution state (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock...
Page 70: Program Execution State
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Exception- Exception- occurs handling handling request complete Program halt state Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence.
Page 71: Memory Map
Section 2 CPU Memory Map Figure 2.16 shows a memory map of the H8/3644 Group. H8/3640 H8/3641 H8/3642 H8/3643 H8/3644 H'0000 Interrupt vectors H'002F 8 kbytes H'0030 H'1FFF 12 kbytes 12 kbytes H'2FFF 24 kbytes H'3FFF 32 kbytes On-chip ROM H'5FFF H'7FFF Reserved...
Page 72: Application Notes
Section 2 CPU Application Notes 2.9.1 Notes on Data Access 1. Access to empty areas The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 73 Section 2 CPU Access States Word Byte H'0000 Interrupt vector area (48 bytes) H'002F H'0030 On-chip ROM H'7FFF — — — Reserved H'F770 Internal I/O registers × (16 bytes) H'F77F Reserved — — — H'FB80 On-chip RAM 1,024 bytes H'FF7F H'FF80 Reserved —...
Page 74: Notes On Bit Manipulation
Section 2 CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O port.
Page 75 Section 2 CPU Example 2: BSET instruction executed designating port 3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P3 to high-level output.
Page 76 Section 2 CPU As a result of this operation, bit 0 in PDR3 becomes 1, and P3 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3.
Page 77 Section 2 CPU Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 78 Section 2 CPU As a result of this operation, bit 0 in PCR3 becomes 0, making P3 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P3 and P3 change from input pins to output pins. To avoid this problem, store a copy of the PCR3 data in a work area in memory.
Page 79 Section 2 CPU Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers that contain write-only bits. Table 2.12 Registers with Shared Addresses Register Name Abbreviation Address Output compare register AH and output compare register BH (timer X) OCRAH/OCRBH H'F774 Output compare register AL and output compare register BL (timer X) OCRAL/OCRBL H'F775 Timer counter B1 and timer load register B1 (timer B1) TCB1/TLB1...
Page 80: Notes On Use Of The Eepmov Instruction
Section 2 CPU 2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 →...
Page 81: Section 3 Exception Handling
Section 3 Exception Handling Section 3 Exception Handling Overview Exception handling is performed in the H8/3644 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority Exception Source Time of Start of Exception Handling...
Page 82 Section 3 Exception Handling Reset exception handling takes place as follows. • The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. • The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC.
Page 83: Interrupt Immediately After Reset
Section 3 Exception Handling Reset by Watchdog Timer: The watchdog timer counter (TCW) starts counting up when the WDON bit is set to 1 in the watchdog timer control/status register (TCSRW). If TCW overflows, the WRST bit is set to 1 in TCSRW and the chip enters the reset state. While the WRST bit is set to 1 in TCSRW, when TCW overflows the reset state is cleared and reset exception handling begins.
Page 84 Section 3 Exception Handling Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt Vector Number Vector Address Priority Reset H'0000 to H'0001 High H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 Timer A Timer A overflow H'0014 to H'0015 Timer B1...
Page 85: Interrupt Control Registers
Section 3 Exception Handling 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Abbreviation Initial Value Address Interrupt edge select register 1 IEGR1 H'70 H'FFF2 Interrupt edge select register 2 IEGR2 H'00 H'FFF3 Interrupt enable register 1...
Page 86 Section 3 Exception Handling Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ Bit 2IRQ Bit 2: IEG2 Description Falling edge of IRQ pin input is detected (initial value) Rising edge of IRQ pin input is detected Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ Bit 1...
Page 87 Section 3 Exception Handling Edge Select (INTEG6): Bit 6 selects the input sensing of the INT Bit 6    INT pin and TMIB pin. Bit 6: INTEG6 Description Falling edge of INT and TMIB pin input is detected (initial value) Rising edge of INT and TMIB pin input is detected...
Page 88 Section 3 Exception Handling Bit 6    Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt requests. Bit 6: IENTA Description Disables timer A interrupt requests (initial value) Enables timer A interrupt requests Bit 5...
Page 89 Section 3 Exception Handling Bit 6    A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter interrupt requests. Bit 6: IENAD Description Disables A/D converter interrupt requests (initial value) Enables A/D converter interrupt requests Bit 5    Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4...
Page 90 Section 3 Exception Handling Interrupt Request Register 1 (IRR1)   IRRTB1 IRRTA IRRI3 IRRI2 IRRI1 IRRI0 Initial value R/W * R/W * R/W * R/W * R/W * R/W *   Read/Write Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer B1, timer A, or IRQ to IRQ...
Page 91 Section 3 Exception Handling Bits 3 to 0    IRQ to IRQ Interrupt Request Flags (IRRI3 to IRRI0) Bit n: IRRIn Description Clearing condition: (initial value) When IRRIn = 1, it is cleared by writing 0 Setting condition: When pin IRQ is designated for interrupt input and the designated signal edge is input...
Page 92 Section 3 Exception Handling Bit 5Reserved bit: Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4SCI1 Interrupt Request Flag (IRRS1) Bit 4: IRRS1 Description Clearing condition: (initial value) When IRRS1 = 1, it is cleared by writing 0 Setting condition: When an SCI1 transfer is completed Bits 3 to 0Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be...
Page 93: External Interrupts
Section 3 Exception Handling 3.3.3 External Interrupts There are 12 external interrupts: IRQ to IRQ and INT to INT are requested by input signals to pins IRQ Interrupts IRQ to IRQ : Interrupts IRQ to IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.
Page 94: Internal Interrupts
Section 3 Exception Handling 3.3.4 Internal Interrupts There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0.
Page 95 Section 3 Exception Handling Interrupt operation is described as follows. • If an interrupt occurs while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. • When the interrupt controller receives an interrupt request, it sets the interrupt request flag. •...
Page 96 Section 3 Exception Handling Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRRI2 = 1 IEN2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ←...
Page 97 Section 3 Exception Handling SP – 4 SP (R7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling...
Page 98 Section 3 Exception Handling Figure 3.5 Interrupt Sequence Rev. 6.00 Sep 12, 2006 page 76 of 526 REJ09B0326-0600...
Page 99: Interrupt Response Time
Section 3 Exception Handling 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Waiting time for completion of executing instruction * 1 to 13 Saving of PC and CCR to stack...
Page 100: Application Notes
Section 3 Exception Handling Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3644 Group, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 101: Notes On Rewriting Port Mode Registers
Section 3 Exception Handling 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ to IRQ , the interrupt request flag may be set to 1 at the time the pin function is...
Page 102 Section 3 Exception Handling Interrupts masked. (Another possibility ← is to disable the relevant interrupt in CCR I bit interrupt enable register 1.) Set port mode register bit After setting the port mode register bit, first execute at least one instruction Execute NOP instruction (e.g., NOP), then clear the interrupt request flag to 0...
Page 103: Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators Section 4 Clock Pulse Generators Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 104: System Clock Generator
Section 4 Clock Pulse Generators System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Connecting a Crystal Resonator: Figure 4.2 shows a typical method of connecting a crystal resonator.
Page 105 Section 4 Clock Pulse Generators Connecting a Ceramic Resonator: Figure 4.4 shows a typical method of connecting a ceramic resonator. Ω R = 1 M ±20% C = 30 pF ±10% C = 30 pF ±10% Ceramic resonator: Murata Figure 4.4 Typical Connection to Ceramic Resonator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic resonator, pay careful attention to the following points.
Page 106: Subclock Generator
Section 4 Clock Pulse Generators External Clock Input Method: Connect an external clock signal to pin OSC , and leave pin open. Figure 4.6 shows a typical connection. External clock input Open Figure 4.6 External Clock Input (Example) Oscillator Clock (φ φ φ φ Frequency Duty cycle 45% to 55%...
Page 107: Prescalers
Section 4 Clock Pulse Generators Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal resonator. C = 1.5 pF (typ.) Ω R = 14 k (typ.) = 32.768 kHz Crystal resonator: MX38T (Nihon Denpa Kogyo) Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Resonator Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X and leave pin X open, as shown in figure 4.9.
Page 108: Note On Oscillators
Section 4 Clock Pulse Generators In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function.
Page 109: Section 5 Power-Down Modes
Section 5 Power-Down Modes Section 5 Power-Down Modes Overview The H8/3644 Group has eight modes of operation after a reset. These include seven power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the eight operating modes.
Page 110 Section 5 Power-Down Modes Program Program Reset state execution state halt state SLEEP instruction Active Sleep (high-speed) (high-speed) Program mode mode halt state Standby mode SLEEP instruction Active Sleep (medium-speed) (medium-speed) mode mode SLEEP SLEEP instruction instruction Watch Subactive Subsleep mode mode mode...
Page 111 Section 5 Power-Down Modes Table 5.2 Internal State in Each Operating Mode Active Mode Sleep Mode High- Medium- High- Medium- Watch Subactive Subsleep Standby Function Speed Speed Speed Speed Mode Mode Mode Mode System clock oscillator Functions Functions Functions Functions Halted Halted Halted...
Page 112: System Control Registers
Section 5 Power-Down Modes 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Registers Name Abbreviation Initial Value Address System control register 1 SYSCR1 H'07 H'FFF0 System control register 2 SYSCR2 H'E0 H'FFF1...
Page 113 Section 5 Power-Down Modes Bits 6 to 4    Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt.
Page 114 Section 5 Power-Down Modes System Control Register 2 (SYSCR2)    NESEL DTON MSON Initial value    Read/Write SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits 7 to 5    Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified.
Page 115 Section 5 Power-Down Modes Bit 3    Direct Transfer on Flag (DTON): This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Page 116: Sleep Mode
Section 5 Power-Down Modes Bits 1 and 0    Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock /2, φ /4, or φ rate (φ /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1: SA1 Bit 0: SA0 Description...
Page 117: Clock Frequency In Sleep (Medium-Speed) Mode
Section 5 Power-Down Modes • Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1.
Page 118: Oscillator Settling Time After Standby Mode Is Cleared
Section 5 Power-Down Modes 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. • When a crystal oscillator is used The table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time of at least 10 ms.
Page 119: Clearing Watch Mode
Section 5 Power-Down Modes 5.4.2 Clearing Watch Mode ) or by input at the RES pin. Watch mode is cleared by an interrupt (timer A or IRQ • Clearing by interrupt When watch mode is cleared by a timer A interrupt or IRQ interrupt, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2.
Page 120: Clearing Subsleep Mode
Section 5 Power-Down Modes 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, IRQ to IRQ , INT to INT ) or by input at the RES pin. • Clearing by interrupt When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Page 121: Operating Frequency In Subactive Mode
Section 5 Power-Down Modes 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are φ /2, φ /4, and φ Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ or IRQ...
Page 122: Direct Transfer
Section 5 Power-Down Modes Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1.
Page 123 Section 5 Power-Down Modes • Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.
Page 124 Section 5 Power-Down Modes Rev. 6.00 Sep 12, 2006 page 102 of 526 REJ09B0326-0600...
Page 125: Section 6 Rom
Section 6 ROM Section 6 ROM Overview The H8/3644 has 32 kbytes of on-chip mask ROM, PROM or flash memory. The H8/3643 has 24 kbytes of mask ROM or flash memory. The H8/3642 has 16 kbytes of mask ROM or flash memory.
Page 126: Prom Mode
Section 6 ROM PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C256 EPROM.
Page 127: Programming
Section 6 ROM Programming The H8/3644 write, verify, and other modes are selected as shown in table 6.2 in PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/3644) Mode to EO to EA Write Data input Address input Verify Data output Address input Programming...
Page 128: Writing And Verifying
Section 6 ROM 6.3.1 Writing and Verifying An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. Data in unused address areas has a value of H'FF. The basic flow of this high-speed, high-reliability programming method is shown in figure 6.3.
Page 129 Section 6 ROM Table 6.3 and table 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Test Item Symbol...
Page 130 Section 6 ROM Table 6.4 AC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C) Item Symbol Unit Test Condition Figure 6.4 *   Address setup time µs OE setup time ...
Page 131: Programming Precautions
) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas Technology specifications for the HN27C256 will result in correct V of 12.5 V.
Page 132: Reliability Of Programmed Data
If a group of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects, using a microcomputer with on-chip EPROM in a windowed package, etc. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 133: Flash Memory Overview
Section 6 ROM Flash Memory Overview 6.4.1 Principle of Flash Memory Operation Table 6.5 illustrates the principle of operation of the on-chip flash memory in the H8/3644F, H8/3643F, and H8/3642AF. Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate.
Page 134: Mode Pin Settings And Rom Space
Section 6 ROM 6.4.2 Mode Pin Settings and ROM Space The H8/3644F has 32 kbytes of on-chip flash memory, the H8/3643F has 24 kbytes, and the H8/3642AF has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses flash memory in two states for both byte-size and word-size instructions.
Page 135: Block Diagram
Section 6 ROM 6.4.4 Block Diagram Figure 6.6 shows a block diagram of the flash memory. Internal data bus (upper) Internal data bus (lower) Operating FLMCR Bus interface/control section TEST mode EBR1 H'0000 H'0001 EBR2 H'0002 H'0003 H'0004 H'0005 On-chip flash memory (32 kbytes) H'7FFC H'7FFD H'7FFE...
Page 136: Pin Configuration
Section 6 ROM 6.4.5 Pin Configuration The flash memory is controlled by means of the pins shown in table 6.6. Table 6.6 Flash Memory Pins Pin Name Abbreviation Input/Output Function Programming power Power supply Apply 12.0 V Mode pin TEST Input Sets H8/3644F operating mode Transmit data...
Page 137: Flash Memory Register Descriptions
Section 6 ROM Flash Memory Register Descriptions 6.5.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this register.
Page 138 Section 6 ROM Bit 2    Program-Verify Mode (PV) * : Bit 2 selects transition to or exit from program-verify mode. Bit 2: PV Description Exit from program-verify mode (initial value) Transition to program-verify mode Note: * Do not set multiple bits simultaneously. Do not release or cut the V or V power supply while a bit is set.
Page 139: Erase Block Register 1 (Ebr1)
Section 6 ROM 6.5.2 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure. EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 V is not applied to FV .
Page 140: Erase Block Register 2 (Ebr2)
Section 6 ROM 6.5.3 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies small flash-memory blocks for programming or erasure. EBR2 is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 V is not applied to FV .
Page 141 Section 6 ROM H'0000 H'0000 SB0 (128 bytes) Small block SB1 (128 bytes) area SB7 to SB0 SB2 (128 bytes) (4 kbytes) (4 kbytes) SB3 (128 bytes) H'0FFF H'01FF H'1000 H'0200 Large block area (H8/3644F: (4 kbytes) (512 bytes) 28 kbytes) H'1FFF H'03FF H'2000...
Page 142: On-Board Programming Modes
Section 6 ROM On-Board Programming Modes When an on-board programming mode is selected, on-chip flash memory programming, erasing, and verifying can be carried out. There are two on-board programming modesboot mode and user program modeset by the mode pin (TEST) and the FV pin.
Page 143 Section 6 ROM Boot Mode Execution Procedure: The boot mode execution procedure is shown below. Start 1. Set the chip to boot mode and execute a reset-start. 2. Set the host to the prescribed bit rate (2400/4800/9600) Set pins to boot mode for chip and have it transmit H'00 data continuously using a and execute reset-start transfer data format of 8-bit data plus 1 stop bit.
Page 144 Section 6 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8/3644F, H8/3643F, or H8/3642AF measures the low period of the asynchronous SCI communication data transmitted continuously from the host (figure 6.10). The data format should be set as 8-bit data, 1 stop bit, no parity.
Page 145 Section 6 ROM Table 6.10 System Clock Oscillation Frequencies Permitting Automatic Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate System Clock Oscillation Frequencies (f ) Permitting Automatic Host Bit Rate * Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate 9600 bps 8 MHz to 16 MHz 4800 bps 4 MHz to 16 MHz...
Page 146 Section 6 ROM Notes on Use of Boot Mode: 1. When the chip (H8/3644F, H8/3643F, or H8/3642AF) comes out of reset in boot mode, it measures the low period of the input at the SCI3’s RXD pin. The reset should end with RXD high.
Page 147: User Program Mode
Section 6 ROM Boot mode can be exited by driving the reset pin low, then releasing 12 V application to the TEST pin and FV pin at least 10 system clock cycles later, and setting the TEST pin to V release the reset.
Page 148 Section 6 ROM User Program Mode Execution Procedure * : The procedure for user program execution in RAM is shown below. Procedure: Reset-start (TEST = V An on-board reprogramming program must be written into flash memory by the user beforehand. 1.
Page 149: Programming And Erasing Flash Memory
Section 6 ROM Programming and Erasing Flash Memory The on-chip flash memory of the H8/3644F, H8/3643F, and H8/3642AF is programmed and erased by software, using the CPU. There are five flash memory operating modes: program mode, erase mode, program-verify mode, erase-verify mode, and prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV, and EV bits in the flash memory control register (FLMCR).
Page 150: Program-Verify Mode
Section 6 ROM 6.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the programming time, exit programming mode (clear the P bit to 0) and select program-verify mode (set the PV bit to 1).
Page 151: Programming Flowchart And Sample Program
Section 6 ROM 6.7.3 Programming Flowchart and Sample Program Flowchart for Programming One Byte Start Set erase block register (set bit for block to be programmed to 1) Write data to flash memory (flash memory latches write address and data) n = 1 Enable watchdog timer Notes: 1.
Page 152 Section 6 ROM Sample Program for Programming One Byte This program uses the following registers: R0H: Used for erase block specification. R1H: Stores programming data. R1L: Stores read data. Stores the programming address. Valid address specifications are H'0000 to H'EF7F. Used for program and program-verify loop counter value setting.
Page 153 Section 6 ROM Set P bit BSET @FLMCR:8 ; LOOP1: SUBS MOV.W R4, Wait loop LOOP1 Clear P bit BCLR @FLMCR:8 ; MOV.B #H'50, Stop watchdog timer MOV.B R4L, @TCSRW:8 ; Set program-verify fail counter MOV.B #H'b, R4H Set PV bit BSET @FLMCR:8 ;...
Page 154: Erase Mode
Section 6 ROM 6.7.4 Erase Mode To erase the flash memory, follow the erasing algorithm shown in figure 6.14. This erasing algorithm enables data to be erased without subjecting the device to voltage stress or impairing the reliability of the programmed data. To erase flash memory, before starting to erase, first place all memory data in all blocks to be erased in the programmed state (program all memory data to H'00).
Page 155: Erase Flowcharts And Sample Programs
Section 6 ROM 6.7.6 Erase Flowcharts and Sample Programs Flowchart for Erasing One Block Start Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite) n = 1 Enable watchdog timer Notes: 1.
Page 156 Section 6 ROM Prewrite Flowchart Start Set erase block register (set bit for block to be programmed to 1) Set start address n = 1 Write H'00 to flash memory Notes: 1. Write using a byte transfer instruction. (flash memory latches programmed address 2.
Page 157 Section 6 ROM Sample Program for Erasing One Block This program uses the following registers: Used for erase block specification. Also stores address used in prewrite and erase-verify. R1H: Stores read data. Also used in dummy write. Stores last address of block to be erased. Stores address used in prewrite and erase-verify.
Page 158 Section 6 ROM Prewrite verify fail counter PREWRT: MOV.B #H'00, Set prewrite loop counter MOV.W #H'a, Prewrite-vector fail counter + 1 → R6L PREWRS: INC MOV.B #H'00, Write H'00 MOV.B R1H, MOV.W #H'FE5A, R4 MOV.B R4L, @TCSRW:8 MOV.B R4H, @TCW:8 MOV.B #H'36, Start watchdog timer MOV.B R4L,...
Page 159 Section 6 ROM Erase-verify fail counter ERASES: MOV.W #H'0000, R6 Set erase loop counter MOV.W #H'd, Erase-verify fail counter + 1 → R6 ERASE: ADDS MOV.W #H'e5A, R4 MOV.B R4L, @TCSRW:8 MOV.B R4H, @TCW:8 MOV.B #H'36, Start watchdog timer MOV.B R4L, @TCSRW:8 Set erase loop counter MOV.W R5,...
Page 160 Section 6 ROM Last address in block? CMP.W R2, EVR2 OKEND Clear EV bit RERASE: BCLR @FLMCR:8 Erase-verify address – 1 → R3 SUBS MOV.W #H'0004, R4 Erase-verify fail count = 4? CMP.W R4, If R6 ≥ 4. branch to BRER (branch until R6 = 4 – 602) BRER If R6 <...
Page 161 Section 6 ROM Flowchart for Erasing Multiple Blocks Start Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite) n = 1 Enable watchdog timer Notes: 1. Program all addresses to be erased by following the prewrite flowchart.
Page 162 Section 6 ROM Sample Program for Erasing Multiple Blocks This program uses the following registers: Used for erase block specification (set as explained below). Also stores address used in prewrite and erase-verify. R1H: Used to test bits 8 to 11 of R0. Stores read data; used in dummy write. R1L: Used to test bits 0 to 11 of R0.
Page 163 Section 6 ROM Notes: 1. In this sample program, the stack pointer (SP) is set to address H'FF80. On-chip RAM addresses H'FF7E and H'FF7F are used as a stack area. Therefore addresses H'FF7E and H'FF7F should not be used when this program is executed, and on-chip RAM should not be disabled.
Page 164 Section 6 ROM Dummy-increment R2 MOV.W @R2+, PRETST ; Execute prewrite Prewrite start address PREWRT: MOV.W @R2+, Prewrite-verify fail counter PREW: MOV.B #H'00, Set prewrite loop counter MOV.W #H'a, Prewrite-verify fail counter + 1 → R6H PREWRS: INC MOV.B #H'00 Write H'00 MOV.B R1H, MOV.W #H'FE5A,...
Page 165 Section 6 ROM MOV.W #H'e5A, MOV.B R4L, @TCSRW:8 ; MOV.B R4H, @TCW:8 MOV.B #H'36, Start watchdog timer MOV.B R4L, @TCSRW:8 ; Set erase loop counter MOV.W R5, Set E bit BSET @FLMCR:8 ; LOOPE: SUBS MOV.W R4, Wait loop LOOPE Clear E bit BCLR @FLMCR:8 ;...
Page 166 Section 6 ROM EVR2: MOV.B #H'FF, Dummy write MOV.B R1H, Set erase-verify loop counter MOV.B #H'c, LOOPEP: DEC Wait loop LOOPEP Read MOV.B @R3+, Read data = H'FF? CMP.B #H'FF, If read data ≠ H'FF, branch to BLKAD BLKAD Start address of next block MOV.W @R2, Last address in block? CMP.W R4,...
Page 167 Section 6 ROM .DATA.W H'2000 ; LB1 .DATA.W H'4000 ; LB2 .DATA.W H'6000 ; LB3 .DATA.W H'8000 ; FLASH END End of erase EOWARI: Erase error ABEND2: Loop Counter and Watchdog Timer Overflow Interval Settings in Programs: The settings of #a, #b, #c, #d, and #e in the program examples depend on the clock frequency.
Page 168 Section 6 ROM Table 6.11 Set Values of #a, #b, #c, and #d for Typical Operating Frequencies when Sample Program Is Executed in On-Chip Memory (RAM) Oscillation Frequency = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz Operating Frequency φ...
Page 169: Prewrite-Verify Mode
Section 6 ROM Examples: Sample calculations when executing a program in on-chip memory (RAM) at an operating frequency of 6 MHz × 9 = 10.8 ≈ 10 = H'000A a (φ) = × ≈ b (φ) = = H'05 × ≈...
Page 170: Protect Modes
Section 6 ROM 6.7.8 Protect Modes There are two modes for flash memory program/erase protection: hardware protection and software protection. These two protection modes are described below. Software Protection: With software protection, setting the P or E bit in the flash memory control register (FLMCR) does not cause a transition to program mode or erase mode.
Page 171: Interrupt Handling During Flash Memory Programming/Erasing
Section 6 ROM Hardware Protection: Hardware protection refers to a state in which programming/erasing of flash memory is forcibly suspended or disabled. At this time, the flash memory control register (FLMCR) and erase block register (EBR1 and EBR2) settings are cleared. Details of the hardware protection states are given below.
Page 172: Flash Memory Prom Mode (H8/3644F, H8/3643F, And H8/3642Af)
Section 6 ROM Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF) 6.8.1 PROM Mode Setting The H8/3644F, H8/3643F, and H8/3642AF, in which the on-chip ROM is flash memory, have a PROM mode as well as the on-board programming modes for programming and erasing flash memory.
Page 173: Operation In Prom Mode
Section 6 ROM 6.8.3 Operation in PROM Mode The program/erase/verify specifications in PROM mode are the same as for the standard HN28F101 flash memory. The H8/3644F, H8/3643F, and H8/3642AF do not have a device recognition code, so the programmer cannot read the device name automatically. Table 6.13 shows how the different operating modes are selected when using PROM mode.
Page 174 Section 6 ROM Table 6.14 PROM Mode Commands 1st Cycle 2nd Cycle Command Cycles Mode Address Data Mode Address Data Memory read Write H'00 Read Dout Erase setup/erase Write H'20 Write H'20 Erase-verify Write H'A0 Read Auto-erase setup/ Write H'30 Write H'30 auto-erase...
Page 175 Section 6 ROM High-Speed, High-Reliability Programming: Unused areas of the flash memory in the H8/3644F, H8/3643F, or H8/3642AF contain H'FF data (initial value). The flash memory uses a high-speed, high-reliability programming procedure. This procedure provides higher programming speed without subjecting the device to voltage stress and without sacrificing the reliability of the programmed data.
Page 176 Section 6 ROM High-Speed, High-Reliability Erasing: The flash memory in the H8/3644F, H8/3643F, and H8/3642AF uses a high-speed, high-reliability erasing procedure. This procedure provides higher erasing speed without subjecting the device to voltage stress and without sacrificing the reliability of data reliability. Figure 6.19 shows the basic high-speed, high-reliability erasing flowchart.
Page 177 Section 6 ROM Table 6.15 DC Characteristics in PROM Mode (Conditions: V = 5.0 V ±10%, V = 12.0 V ±0.6 V, V = 0 V, T = 25°C ±5°C) Item Symbol Min Unit Test Conditions  Input high to FO , FA to FA + 0.3 V...
Page 178 Section 6 ROM Table 6.16 AC Characteristics in PROM Mode (Conditions: V = 5.0 V ±10%, V = 12.0 V ±0.6 V, V = 0 V, T = 25°C ±5°C) Test Item Symbol Unit Conditions   Command write cycle Figure 6.20 Figure 6.21 * ...
Page 179 Section 6 ROM Auto-erase Auto-erase setup and status polling 5.0 V 12 V 5.0 V Address OEPS OEWS Command Command I/O7 input input Status polling Command Command I/O0 to I/O6 input input Figure 6.20 Auto-Erase Timing Rev. 6.00 Sep 12, 2006 page 157 of 526 REJ09B0326-0600...
Page 180 Section 6 ROM Program setup Program Program-verify 5.0 V 12 V 5.0 V Address Valid address OERS OEWS Valid data Command Command I/O7 Command input input input output Valid data Command Command Command I/O0 to I/O6 input input input output Note: Program-verify data output values maybe intermediate between 1 and 0 if programming is insufficient.
Page 181 Section 6 ROM Erase setup Erase Erase -verify 5.0 V 12 V 5.0 V Valid address Address OEWS OERS Valid data I/O0 to I/O7 Command Command Command input input input output Note: Erase -verify data output values maybe intermediate between 1 and 0 if erasing is insufficient. Figure 6.22 Erase Timing Rev.
Page 182: Flash Memory Programming And Erasing Precautions
The rated programming voltage (V ) of the flash memory is 12.0 V. If the PROM programmer is set to Renesas HN28F101 specifications, V will be 12.0 V. Applied voltages in excess of the rating can permanently damage the device. In particular, insure that the peak overshoot of the PROM programmer does not exceed the maximum rating of 13 V.
Page 183 Section 6 ROM • Oscillation must have stabilized (following the elapse of the oscillation settling time) or be stopped. power is turned on, hold the RES pin low for the duration of the When the V oscillation settling time * = 20 ms) before applying V •...
Page 184 Section 6 ROM OSC1 φ 3.0 to 5.5 V 0 µs min. 0 µs min. 12 ±0.6 V + 2 V to 11.4 V 0 µs min. 0 to V Timing of boot program branch (boot mode) to RAM space 12 ±0.6 V 0 to V (user program...
Page 185 Section 6 ROM 7. Design a current margin into the programming voltage (V ) power supply. Insure that V remains within the range 12.0 V ±0.6 V (11.4 V to 12.6 V) during programming and erasing. Programming and erasing may become impossible outside this range.
Page 186 Section 6 ROM the 0 or 1 status of this bit. A byte data comparison is necessary to check whether 12V is being applied. The relevant coding is shown below. LABEL1: MOV.B @H'FF80, R1L CMP.B #H'FF, R1L LABEL1 Sample program for detection of 12 V application to FV (user mode) Table 6.17 Flash Memory DC Characteristics...
Page 187 Section 6 ROM Table 6.18 Flash Memory AC Characteristics = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, AV = 3.0 V to AV = AV = 0 V, = 12.0 V ±0.6 V = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 188 Section 6 ROM Rev. 6.00 Sep 12, 2006 page 166 of 526 REJ09B0326-0600...
Page 189: Section 7 Ram
Section 7 RAM Section 7 RAM Overview The H8/3644 Group has 1 kbyte and 512 byte of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 190 Section 7 RAM Rev. 6.00 Sep 12, 2006 page 168 of 526 REJ09B0326-0600...
Page 191: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Overview The H8/3644 Group is provided with three 8-bit I/O ports, three 5-bit I/O ports, two 3-bit I/O ports, and one 8-bit input-only port. Table 8.1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data.
Page 192 Section 8 I/O Ports Function Switching Port Description Pins Other Functions Register • Port 6 to P6 8-bit I/O port • High-current port • Port 7 5-bit I/O port /TMOV Timer V compare-match TCSRV output /TMCIV Timer V clock input /TMRIV Timer V reset input •...
Page 193: Port 1
Section 8 I/O Ports Port 1 8.2.1 Overview Port 1 is a 5-bit I/O port. Figure 8.1 shows its pin configuration. P1 /IRQ /TRGV P1 /IRQ P1 /IRQ Port 1 P1 /PWM P1 /TMOW Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration.
Page 194 Section 8 I/O Ports PDR1 is an 8-bit register that stores data for port 1 pins P1 through P1 and P1 . If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Page 195 Section 8 I/O Ports Port Mode Register 1 (PMR1)    IRQ3 IRQ2 IRQ1 TMOW Initial value    Read/Write PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'04. Bit 7...
Page 196 Section 8 I/O Ports Bit 4    P1 /PWM Pin Function Switch (PWM): This bit selects whether pin P1 /PWM is used as P1 or as PWM. Bit 4: PWM Description Functions as P1 I/O pin (initial value) Functions as PWM output pin Bit 3...
Page 197: Pin Functions
Section 8 I/O Ports 8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TRGV The pin function depends on bit IRQ3 in PMR1 and bit PCR1 in PCR1.
Page 198: Pin States
Section 8 I/O Ports 8.2.4 Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ /TRGV High- Retains Retains High- Retains Functional Functional impedance * impedance...
Page 199: Port 2
Section 8 I/O Ports Port 2 8.3.1 Overview Port 2 is a 3-bit I/O port, configured as shown in figure 8.2. P2 /TXD P2 /RXD Port 2 P2 /SCK Figure 8.2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration.
Page 200 Section 8 I/O Ports Port Control Register 2 (PCR2)      PCR2 PCR2 PCR2 Initial value      Read/Write PCR2 is an 8-bit register for controlling whether each of the port 1 pins P2 to P2 functions as an input pin or output pin.
Page 201: Pin Functions
Section 8 I/O Ports 8.3.3 Pin Functions Table 8.6 shows the port 2 pin functions. Table 8.6 Port 2 Pin Functions Pin Functions and Selection Method /TXD The pin function depends on bit TXD in PMR7 and bit PCR2 in PCR2. PCR2 Pin function input pin P2...
Page 202: Port 3
Section 8 I/O Ports Port 3 8.4.1 Overview Port 3 is a 8-bit I/O port, configured as shown in figure 8.3. P3 /SO P3 /SI Port 3 P3 /SCK Figure 8.3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8.8 shows the port 3 register configuration.
Page 203 Section 8 I/O Ports Upon reset, PDR3 is initialized to H'00. Port Control Register 3 (PCR3)      PCR3 PCR3 PCR3 Initial value      Read/Write PCR3 is an 8-bit register for controlling whether each of the port 3 pins P3 to P3 functions as an input pin or output pin.
Page 204 Section 8 I/O Ports PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00. Bits 7 to 3    Reserved Bits: Bits 7 to 3 are reserved: they are always read as 0 and cannot be modified.
Page 205 Section 8 I/O Ports Bits 7 to 3    Reserved Bits: Bits 7 to 3 are reserved; they are always read as 1, and cannot be modified. Bit 2    P2 /TXD Pin Function Switch (TXD): Bit 2 selects whether pin P2 /TXD is used as P2 or as TXD.
Page 206: Pin Functions
Section 8 I/O Ports 8.4.3 Pin Functions Table 8.9 shows the port 3 pin functions. Table 8.9 Port 3 Pin Functions Pin Functions and Selection Method The pin function depends on bit SO1 in PMR3 and bit PCR3 in PCR3. PCR3 Pin function input pin P3...
Page 207: Pin States
Section 8 I/O Ports 8.4.4 Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active High- Retains Retains High- Retains Functional Functional impedance * impedance previous...
Page 208: Port 5
Section 8 I/O Ports Port 5 8.5.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.4. /INT /INT /TMIB /INT /ADTRG /INT Port 5 /INT /INT /INT /INT Figure 8.4 Port 5 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 5 register configuration.
Page 209 Section 8 I/O Ports Port Data Register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 210: Pin Functions
Section 8 I/O Ports 8.5.3 Pin Functions Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions Pin Functions and Selection Method /INT The pin function depends on bit PCR5 in PCR5. PCR5 Pin function input pin output pin input pin /INT...
Page 211: Pin States
Section 8 I/O Ports 8.5.4 Pin States Table 8.13 shows the port 5 pin states in each operating mode. Table 8.13 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /INT High- Retains Retains High- Retains Functional Functional impedance * /INT impedance...
Page 212: Port 6
Section 8 I/O Ports Port 6 8.6.1 Overview Port 6 is an 8-bit large-current I/O port, with a maximum sink current of 10 mA. The port 6 pin configuration is shown in figure 8.5. Port 6 Figure 8.5 Port 6 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 6 register configuration.
Page 213: Pin Functions
Section 8 I/O Ports PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 When a bit in PCR6 is set to 1, if port 6 is read the value of the corresponding PDR6 bit is returned directly regardless of the pin state.
Page 214: Pin States
Section 8 I/O Ports 8.6.4 Pin States Table 8.16 shows the port 6 pin states in each operating mode. Table 8.16 Port 6 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active toP6 High- Retains Retains High- Retains Functional Functional impedance * impedance previous...
Page 215 Section 8 I/O Ports Port Data Register 7 (PDR7)    Initial value    Read/Write Note: * Bits 2 to 0 are reserved; they are always read as 0 and cannot be modified. PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 .
Page 216: Pin Functions
Section 8 I/O Ports 8.7.3 Pin Functions Table 8.18 shows the port 7 pin functions. Table 8.18 Port 7 Pin Functions Pin Functions and Selection Method , P7 The pin function depends on bit PCR7 in PCR7. (n = 7 or 3) PCR7 Pin function input pin...
Page 217: Pin States
Section 8 I/O Ports 8.7.4 Pin States Table 8.19 shows the port 7 pin states in each operating mode. Table 8.19 Port 7 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active to P7 High- Retains Retains High- Retains Functional Functional impedance previous...
Page 218: Register Configuration And Description
Section 8 I/O Ports 8.8.2 Register Configuration and Description Table 8.20 shows the port 8 register configuration. Table 8.20 Port 8 Registers Name Abbr. Initial Value Address Port data register 8 PDR8 H'00 H'FFDB Port control register 8 PCR8 H'00 H'FFEB Port Data Register 8 (PDR8) Initial value...
Page 219: Pin Functions
Section 8 I/O Ports 8.8.3 Pin Functions Table 8.21 shows the port 8 pin functions. Table 8.21 Port 8 Pin Functions Pin Functions and Selection Method The pin function depends on bit PCR8 in PCR8. PCR8 Pin function input pin output pin /FTID The pin function depends on bit PCR8...
Page 220: Pin States
Section 8 I/O Ports Pin Functions and Selection Method /FTOA The pin function depends on bit PCR8 in PCR8 and bit OEA in TOCR. PCR8 Pin function input pin P8 output pin FTOA output pin /FTCI The pin function depends on bit PCR8 in PCR8.
Page 221: Port 9
Section 8 I/O Ports Port 9 8.9.1 Overview Port 9 is a 5-bit I/O port, configured as shown in figure 8.8. Port 9 P9 * Note: * There is no P9 function in the flash memory version since P9 is used as the FV pin.
Page 222: Pin Functions
Section 8 I/O Ports PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
Page 223: Pin States
Section 8 I/O Ports 8.9.4 Pin States Table 8.25 shows the port 9 pin states in each operating mode. Table 8.25 Port 9 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active to P9 High- Retains Retains High- Retains Functional Functional impedance previous...
Page 224: Pin Functions
Section 8 I/O Ports Port Data Register B (PDRB) Read/Write Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage.
Page 225: Section 9 Timers
Section 9 Timers Section 9 Timers Overview The H8/3644 Group provides five timers: timers A, B1, V, X, and a watchdog timer. The functions of these timers are outlined in table 9.1. Table 9.1 Timer Functions Event Waveform Name Functions Internal Clock Input Pin Output Pin Remarks...
Page 226: Timer A
Section 9 Timers Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal resonator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. Features Features of timer A are given below.
Page 227 Section 9 Timers Block Diagram Figure 9.1 shows a block diagram of timer A. φ φ /4 φ /32 φ /16 φ /8 φ /4 φ /128 TMOW φ/32 φ/8192, φ/4096, φ/2048, φ/16 φ/512, φ/256, φ/128, φ/8 φ/32, φ/8 φ/4 φ...
Page 228: Register Descriptions
Section 9 Timers Register Configuration Table 9.3 shows the register configuration of timer A. Table 9.3 Timer A Registers Name Abbr. Initial Value Address Timer mode register A H'10 H'FFB0 Timer counter A H'00 H'FFB1 9.2.2 Register Descriptions Timer Mode Register A (TMA) ...
Page 229 Section 9 Timers Bit 4    Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0    Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Page 230: Timer Operation
Section 9 Timers TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. 9.2.3 Timer Operation Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer.
Page 231: Timer A Operation States
Section 9 Timers 9.2.4 Timer A Operation States Table 9.4 summarizes the timer A operation states. Table 9.4 Timer A Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby TCA Interval Reset Functions Functions Halted Halted Halted Halted Clock time base Reset Functions Functions Functions Functions Functions Halted...
Page 232 Section 9 Timers Block Diagram Figure 9.2 shows a block diagram of timer B1. TMB1 φ TCB1 TLB1 TMIB IRRTB1 Legend: TMB1: Timer mode register B1 TCB1: Timer counter B1 TLB1: Timer load register B1 IRRTB1: Timer B1 interrupt request flag PSS: Prescaler S Figure 9.2 Block Diagram of Timer B1...
Page 233: Register Descriptions
Section 9 Timers Register Configuration Table 9.6 shows the register configuration of timer B1. Table 9.6 Timer B1 Registers Name Abbr. Initial Value Address Timer mode register B1 TMB1 H'78 H'FFB2 Timer counter B1 TCB1 H'00 H'FFB3 Timer load register B1 TLB1 H'00 H'FFB3...
Page 234 Section 9 Timers Bits 2 to 0    Clock Select (TMB12 to TMB10): Bits 2 to 0 select the clock input to TCB1. For external event counting, either the rising or falling edge can be selected. Bit 2: TMB12 Bit 1: TMB11 Bit 0: TMB10 Description...
Page 235: Timer Operation
Section 9 Timers Timer Load Register B1 (TLB1) TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10 Initial value Read/Write TLB1 is an 8-bit write-only register for setting the reload value of timer counter B1 (TCB1). When a reload value is set in TLB1, the same value is loaded into timer counter B1 (TCB1) as well, and TCB1 starts counting up from that value.
Page 236: Timer B1 Operation States
Section 9 Timers Auto-Reload Timer Operation: Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow.
Page 237: Timer V
Section 9 Timers Timer V 9.4.1 Overview Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Also compare match signals can be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle.
Page 238 Section 9 Timers Block Diagram Figure 9.3 shows a block diagram of timer V. TCRV1 TCORB Trigger TRGV control Comparator TMCIV Clock select TCNTV Comparator φ TCORA Clear control TMRIV TCRV0 Interrupt request control Output TMOV TCSRV control CMIA Legend: CMIB TCORA: Time constant register A...
Page 239 Section 9 Timers Pin Configuration Table 9.8 shows the timer V pin configuration. Table 9.8 Pin Configuration Name Abbr. Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV...
Page 240: Register Descriptions
Section 9 Timers 9.4.2 Register Descriptions Timer Counter V (TCNTV) TCNTV TCNTV TCNTV TCNTV TCNTV TCNTV TCNTV TCNTV Initial value Read/Write TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input. The clock source is selected by bits CKS2 to CKS0 in TCRV0. The TCNTV value can be read and written by the CPU at any time.
Page 241 Section 9 Timers Timer Control Register V0 (TCRV0) CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of TCNTV, and enables interrupts. TCRV0 is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode.
Page 242 Section 9 Timers If TRGE is cleared to 0, after TCNTV is cleared it continues counting up. Bit 4: CCLR1 Bit 3: CCLR0 Description Clearing is disabled (initial value) Cleared by compare match A Cleared by compare match B Cleared by rising edge of external reset input Bits 2 to 0...
Page 243 Section 9 Timers Timer Control/Status Register V (TCSRV)  CMFB CMFA Initial value R/(W) * R/(W) * R/(W) *  Read/Write Note: * Bits 7 to 5 can be only written with 0, for flag clearing. TCSRV is an 8-bit register that sets compare match flags and the timer overflow flag, and controls compare match output.
Page 244 Section 9 Timers Bit 5    Timer Overflow Flag (OVF): Bit 5 is a status flag indicating that TCNTV has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software.
Page 245 Section 9 Timers Timer Control Register V1 (TCRV1)     TVEG1 TVEG0 TRGE ICKS0 Initial value     Read/Write TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV.
Page 246: Timer Operation
Section 9 Timers 9.4.3 Timer Operation Timer V Operation: A reset initializes TCNTV to H'00, TCORA and TCORB to H'FF, TCRV0 to H'00, TCSRV to H'10, and TCRV1 to H'E2. Timer V can be clocked by one of six internal clocks output from prescaler S, or an external clock, as selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1.
Page 247 Section 9 Timers TCNTV Increment Timing: TCNTV is incremented by an input (internal or external) clock. • Internal clock One of six clocks (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) divided from the system clock (φ) can be selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. Figure 9.4 shows the timing.
Page 248 Section 9 Timers φ TMCIV (external clock input pin) TCNTV input clock N – 1 N – 1 TCNTV Figure 9.5 Increment Timing with External Clock Overflow flag Set Timing: The overflow flag (OVF) is set to 1 when TCNTV overflows from H'FF to H'00.
Page 249 Section 9 Timers Compare Match Flag set Timing: Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB. The internal compare-match signal is generated in the last state in which the values match (when TCNTV changes from the matching value to a new value).
Page 250 Section 9 Timers TCNTV Clear Timing by Compare Match: TCNTV can be cleared by compare match A or B, as selected by bits CCLR1 and CCLR0 in TCRV0. Figure 9.9 shows the timing. φ Compare match A signal TCNTV H'00 Figure 9.9 Clear Timing by Compare Match TCNTV Clear Timing by TMRIV: TCNTV can be cleared by a rising edge at the TMRIV pin, as selected by bits CCLR1 and CCLR0 in TCRV0.
Page 251: Timer V Operation Modes
Section 9 Timers 9.4.4 Timer V Operation Modes Table 9.10 summarizes the timer V operation states. Table 9.10 Timer V Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby TCNTV Reset Functions Functions Reset Reset Reset Reset TCRV0, TCRV1 Reset...
Page 252 Section 9 Timers With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB. TCNTV H'FF Counter cleared TCORA TCORB H'00 TMOV Figure 9.11 Pulse Output Example Single-Shot Output with Arbitrary Pulse Width and Delay from TRGV Input: The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 9.12.
Page 253 Section 9 Timers After these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB – TCORA). TCNTV H'FF Counter cleared TCORB TCORA H'00 TRGV...
Page 254: Application Notes
Section 9 Timers 9.4.7 Application Notes The following types of contention can occur in timer V operation. Contention between TCNTV Write and Counter Clear: If a TCNTV clear signal is generated in the T state of a TCNTV write cycle, clearing takes precedence and the write to the counter is not carried out.
Page 255 Section 9 Timers Contention between TCNTV Write and Increment: If a TCNTV increment clock signal is generated in the T state of a TCNTV write cycle, the write takes precedence and the counter is not incremented. Figure 9.14 shows the timing. TCNTV write cycle by CPU φ...
Page 256 Section 9 Timers Contention between TCOR Write and Compare Match: If a compare match is generated in the state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 9.15 shows the timing. TCORA write cycle by CPU φ...
Page 257 Section 9 Timers Contention between Compare Match A and B: If compare match A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by following the priority order in table 9.12. Table 9.12 Timer Output Priority Order Output Setting Priority...
Page 258 Section 9 Timers Table 9.13 Internal Clock Switching and TCNTV Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCNTV Operation Goes from low level Clock before to low level * switching Clock after switching Count clock N + 1 TCNTV Write to CKS1 and CKS0 Goes from low...
Page 259 Section 9 Timers Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCNTV Operation Goes from high level Clock before to low level * switching Clock after switching Count clock N + 1 N + 2 TCNTV Write to CKS1 and CKS0 Goes from high Clock before to high...
Page 260: Timer X
Section 9 Timers Timer X 9.5.1 Overview Timer X is based on a 16-bit free-running counter (FRC). It can output two independent waveforms, or measure input pulse widths and external clock periods. Features Features of timer X are given below. •...
Page 261 Section 9 Timers Block Diagram Figure 9.16 shows a block diagram of timer X. ICRA FTIA Input ICRC FTIB capture FTIC control ICRB FTID ICRD TCRX OCRB Comparator FTCI Comparator OCRA φ FTOA TOCR FTOB TCSRX TIER Interrupt request Legend: TIER: Timer interrupt enable register TCSRX:...
Page 262 Section 9 Timers Pin Configuration Table 9.14 shows the timer X pin configuration. Table 9.14 Pin Configuration Name Abbr. Function Counter clock input FTCI Input Clock input to FRC Output compare A FTOA Output Output pin for output compare A Output compare B FTOB Output...
Page 263 Section 9 Timers Register Configuration Table 9.15 shows the register configuration of timer X. Table 9.15 Timer X Registers Name Abbr. Initial Value Address Timer interrupt enable register TIER H'01 H'F770 R/(W) * Timer control/status register X TCSRX H'00 H'F771 Free-running counter H FRCH H'00...
Page 264: Register Descriptions
Section 9 Timers 9.5.2 Register Descriptions Free-Running Counter (FRC) Free-Running Counter H (FRCH) Free-Running Counter L (FRCL) Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRCH FRCL FRC is a 16-bit read/write up-counter, which is incremented by internal or external clock input. The clock source is selected by bits CKS1 and CKS0 in TCRX.
Page 265 Section 9 Timers There are two 16-bit read/write output compare registers, OCRA and OCRB, the contents of which are always compared with FRC. When the values match, OCFA or OCFB is set to 1 in TCSRX. If OCIAE = 1 or OCIBE = 1 in TIER, a CPU interrupt is requested. When a compare match with OCRA or OCRB occurs, if OEA = 1 or OEB = 1 in TOCR, the value selected by OLVLA or OLVLB in TOCR is output at the FTOA or FTOB pin.
Page 266 Section 9 Timers external input signal can be selected simultaneously, by setting IEDGA ≠ IEDGC. If IEDGA = IEDGC, then only one edge is selected (either the rising edge or falling edge). See table 9.16. Note: The FRC value is transferred to the input capture register (ICR) regardless of the value of the input capture flag (ICF).
Page 267 Section 9 Timers Timer Interrupt Enable Register (TIER)  ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE Initial value  Read/Write TIER is an 8-bit read/write register that enables or disables interrupt requests. TIER is initialized to H'01 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode.
Page 268 Section 9 Timers Bit 4    Input Capture Interrupt D Enable (ICIDE): Bit 4 enables or disables the ICID interrupt requested when ICFD is set to 1 in TCSRX. Bit 4: ICIDE Description Interrupt request by ICFD (ICID) is disabled (initial value) Interrupt request by ICFD (ICID) is enabled Bit 3...
Page 269 Section 9 Timers Timer Control/Status Register X (TCSRX) ICFA ICFB ICFC ICFD OCFA OCFB CCLRA Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Note: * Bits 7 to 1 can only be written with 0 for flag clearing. TCSRX is an 8-bit register that selects clearing of the counter and controls interrupt request signals.
Page 270 Section 9 Timers Bit 5    Input Capture Flag C (ICFC): Bit 5 is a status flag that indicates that the FRC value has been transferred to ICRC by an input capture signal. If BUFEA is set to 1 in TCRX, ICFC is set by the input capture signal even though the FRC value is not transferred to ICRC.
Page 271 Section 9 Timers Bit 2    Output Compare Flag B (OCFB): Bit 2 is a status flag that indicates that the FRC value has matched OCRB. This flag is set by hardware and cleared by software. It cannot be set by software.
Page 272 Section 9 Timers Timer Control Register X (TCRX) IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value Read/Write TCRX is an 8-bit read/write register that selects the valid edges of the input capture signals, enables buffering, and selects the FRC clock source. TCRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode.
Page 273 Section 9 Timers Bit 4    Input Edge Select D (IEDGD): Bit 4 selects the rising or falling edge of the input capture D input signal (FTID). Bit 4: IEDGD Description Falling edge of input capture D is captured (initial value) Rising edge of input capture D is captured Bit 3...
Page 274 Section 9 Timers Timer Output Compare Control Register (TOCR)    OCRS OLVLA OLVLB Initial value    Read/Write TOCR is an 8-bit read/write register that selects the output compare output levels, enables output compare output, and controls access to OCRA and OCRB. TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode.
Page 275: Cpu Interface
Section 9 Timers Bit 1    Output Level A (OLVLA): Bit 1 selects the output level that is output at pin FTOA by compare match A (when FRC matches OCRA). Bit 1: OLVLA Description Low level (initial value) High level Bit 0...
Page 276 Section 9 Timers Write Access: Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9.18 shows an example of the writing of H'AA55 to FRC.
Page 277 Section 9 Timers Read Access: In access to FRC and ICRA to ICRD, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRA or OCRB, when the upper byte is read the upper-byte data is transferred directly to the CPU, and when the lower byte is read the lower-byte data is transferred directly to the CPU.
Page 278: Timer Operation
Section 9 Timers 9.5.4 Timer Operation Timer X Operation • Output compare operation Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources or an external clock for input to FRC. The FRC contents are compared constantly with OCRA and OCRB.
Page 279 Section 9 Timers FRC Count Timing: FRC is incremented by clock input. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources (φ/2, φ/8, φ/32) or an external clock. • Internal clock Bits CKS1 and CKS0 in TCRX select one of three internal clock sources (φ/2, φ/8, φ/32) created by dividing the system clock (φ).
Page 280 Section 9 Timers Output Compare Timing: When a compare match occurs, the output level selected by the OLVL bit in TOCR is output at pin FTOA or FTOB. Figure 9.22 shows the output timing for output compare A. φ N + 1 N + 1 OCRA Compare...
Page 281 Section 9 Timers Input Capture Timing • Input capture timing The rising or falling edge is selected for input capture by bits IEDGA to IEDGD in TCRX. Figure 9.24 shows the timing when the rising edge is selected (IEDGA/B/C/D = 1). φ...
Page 282 Section 9 Timers • Buffered input capture timing Input capture can be buffered by using ICRC or ICRD as a buffer for ICRA or ICRB. Figure 9.26 shows the timing when ICRA is buffered by ICRC (BUFEA = 1) and both the rising and falling edges are selected (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1).
Page 283 Section 9 Timers ICRA or ICRC upper byte read cycle by CPU φ FTIA Input capture signal Figure 9.27 Buffered Input Capture Signal Timing (during ICRA or ICRD Read) Input Capture Flag (ICFA to ICFD) Set Timing: Figure 9.28 shows the timing when an input capture flag (ICFA to ICFD) is set to 1 and the FRC value is transferred to the corresponding input capture register (ICRA to ICRD).
Page 284 Section 9 Timers Output Compare Flag (OCFA or OCFB) Set Timing: OCFA and OCFB are set to 1 by internal compare match signals that are output when FRC matches OCRA or OCRB. The compare match signal is generated in the last state during which the values match (when FRC is updated from the matching value to a new value).
Page 285: Timer X Operation Modes
Section 9 Timers 9.5.5 Timer X Operation Modes Table 9.17 shows the timer X operation modes. Table 9.17 Timer X Operation Modes Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby Reset Functions Functions Reset Reset Reset Reset OCRA, OCRB Reset Functions...
Page 286: Timer X Application Example
Section 9 Timers 9.5.7 Timer X Application Example Figure 9.31 shows an example of the output of pulse signals with a 50% duty cycle and arbitrary phase offset. To set up this output: • Set bit CCLRA to 1 in TCSRX. •...
Page 287: Application Notes
Section 9 Timers 9.5.8 Application Notes The following types of contention can occur in timer X operation. 1. Contention between FRC write and counter clear If an FRC clear signal is generated in the T state of a write cycle to the lower byte of FRC, clearing takes precedence and the write to the counter is not carried out.
Page 288 Section 9 Timers 2. Contention between FRC write and increment If an FRC increment clock signal is generated in the T state of a write cycle to the lower byte of FRC, the write takes precedence and the counter is not incremented. Figure 9.33 shows the timing.
Page 289 Section 9 Timers 3. Contention between OCR write and compare match If a compare match is generated in the T state of a write cycle to the lower byte of OCRA or OCRB, the write to OCRA or OCRB takes precedence and the compare match signal is inhibited.
Page 290 Section 9 Timers 4. Internal clock switching and counter operation Depending on the timing, FRC may be incremented by a switch between different internal clock sources. Table 9.19 shows the relation between internal clock switchover timing (by writing to bits CKS1 and CKS0) and FRC operation. When FRC is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, which is divided from the system clock (φ).
Page 291 Section 9 Timers Clock Levels Before and After Modifying Bits CKS1 and CKS0 FRC Operation Goes from high level Clock before to low level switching Clock after switching Count clock N + 1 N + 2 Write to CKS1 and CKS0 Goes from high to high Clock before switching...
Page 292: Watchdog Timer
Section 9 Timers Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. Features Features of the watchdog timer are given below.
Page 293: Register Descriptions
Section 9 Timers Register Configuration Table 9.20 shows the register configuration of the watchdog timer. Table 9.20 Watchdog Timer Registers Name Abbr. Initial Value Address Timer control/status register W TCSRW H'AA H'FFBE Timer counter W H'00 H'FFBF 9.6.2 Register Descriptions Timer Control/Status Register W (TCSRW) B6WI TCWE...
Page 294 Section 9 Timers Bit 5    Bit 4 Write Inhibit (B4WI): Bit 5 controls the writing of data to bit 4 in TCSRW. This bit is always read as 1. Data written to this bit is not stored. Bit 5: B4WI Description Bit 4 is write-enabled...
Page 295 Section 9 Timers Bit 1    Bit 0 Write Inhibit (B0WI): Bit 1 controls the writing of data to bit 0 in TCSRW. This bit is always read as 1. Data written to this bit is not stored. Bit 1: B0WI Description Bit 0 is write-enabled...
Page 296: Timer Operation
Section 9 Timers 9.6.3 Timer Operation The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (φ/8192). When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up (two write accesses to TCSRW are necessary in order to operate the watchdog timer).
Page 297: Watchdog Timer Operation States
Section 9 Timers 9.6.4 Watchdog Timer Operation States Table 9.21 summarizes the watchdog timer operation states. Table 9.21 Watchdog Timer Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby Reset Functions Functions Halted Halted Halted Halted TCSRW Reset Functions...
Page 298 Section 9 Timers Rev. 6.00 Sep 12, 2006 page 276 of 526 REJ09B0326-0600...
Page 299: Section 10 Serial Communication Interface
Section 10 Serial Communication Interface Section 10 Serial Communication Interface 10.1 Overview The H8/3644 Group is provided with a two-channel serial communication interface (SCI). Table 10.1 summarizes the functions and features of the two SCI channels. Table 10.1 Serial Communication Interface Functions Channel Functions Features...
Page 300 Section 10 Serial Communication Interface Features • Choice of 8-bit or 16-bit data length • Choice of eight internal clock sources (φ/1024, φ/256, φ/64, φ/32, φ/16, φ/8, φ/4, φ/2) or an external clock • Interrupt requested at completion of transfer •...
Page 301: Register Descriptions
Section 10 Serial Communication Interface Pin Configuration Table 10.2 shows the SCI1 pin configuration. Table 10.2 Pin Configuration Name Abbr. Function SCI1 clock pin SCI1 clock input or output SCI1 data input pin Input SCI1 receive data input SCI1 data output pin Output SCI1 transmit data output Register Configuration...
Page 302 Section 10 Serial Communication Interface Bits 7 and 6    Operation Mode Select 1, 0 (SNC1, SNC0): Bits 7 and 6 select the operation mode. Bit 7: SNC1 Bit 6: SNC0 Description 8-bit synchronous transfer mode (initial value) 16-bit synchronous transfer mode Continuous clock output mode * Reserved *...
Page 303 Section 10 Serial Communication Interface Bits 2 to 0    Clock Select (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. Serial Clock Cycle φ φ φ φ = 5 MHz φ...
Page 304 Section 10 Serial Communication Interface Bit 6    Extended Data Bit (SOL): Bit 6 sets the SO output level. When read, SOL returns the output level at the SO pin. After completion of a transmission, SO continues to output the value of the last bit of transmitted data.
Page 305 Section 10 Serial Communication Interface Bit 0    Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared to 0 upon completion of the transfer.
Page 306: Operation In Synchronous Mode
Section 10 Serial Communication Interface SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits). In 8-bit transfer, data written to SDRL is output from pin SO starting from the least significant bit (LSB).
Page 307 Section 10 Serial Communication Interface Data Transfer Operations Transmitting: A transmit operation is carried out as follows. 1. Set bits SO1 and SCK1 to 1 in PMR3 to select the SO and SCK pin functions. If necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO 2.
Page 308 Section 10 Serial Communication Interface After data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the SCSR1 overrun error flag (bit ORER) is set to 1. Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as follows.
Page 309: Operation In Ssb Mode
Section 10 Serial Communication Interface 10.2.4 Operation in SSB Mode SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables multiple ICs to be connected as shown in figure 10.3. In SSB mode, TAIL MARK is sent after an 8- or 16-bit data transfer. HOLD TAIL or LATCH TAIL can be selected as TAIL MARK.
Page 310 Section 10 Serial Communication Interface TAIL MARK: TAIL MARK can be either HOLD TAIL or LATCH TAIL. The output waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10.5. Time t in the figure is determined by the transfer clock cycle set in bits CKS2 to CKS0 in SCR1. <...
Page 311: Interrupts
Section 10 Serial Communication Interface 10.2.5 Interrupts SCI1 can generate an interrupt at the end of a data transfer. When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1. SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 2 (IENR2).
Page 312 Section 10 Serial Communication Interface  Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length 8 bits Receive error detection Overrun errors •...
Page 313 Section 10 Serial Communication Interface Block Diagram Figure 10.6 shows a block diagram of SCI3. Internal clock (φ/64, φ/16, φ/4, φ) External Baud rate generator clock Clock Transmit/receive SCR3 control circuit Interrupt request (TEI, TXI, RXI, ERI) Legend: RSR: Receive shift register RDR: Receive data register TSR:...
Page 314: Register Descriptions
Section 10 Serial Communication Interface Pin Configuration Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name Abbr. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output Register Configuration Table 10.5 shows the SCI3 register configuration.
Page 315 Section 10 Serial Communication Interface RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically.
Page 316 Section 10 Serial Communication Interface Transmit Data Register (TDR) TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission.
Page 317 Section 10 Serial Communication Interface Bit 6    Character Length (CHR): Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting.
Page 318 Section 10 Serial Communication Interface Bit 3    Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added.
Page 319 Section 10 Serial Communication Interface Serial Control Register 3 (SCR3) MPIE TEIE CKE1 CKE0 Initial value Read/Write SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. SCR3 can be read or written by the CPU at any time.
Page 320 Section 10 Serial Communication Interface Bit 5    Transmit Enable (TE): Bit 5 selects enabling or disabling of the start of transmit operation. Bit 5: TE Description Transmit operation disabled * (TXD pin is transmit data pin) * (initial value) Transmit operation enabled * (TXD pin is transmit data pin) *...
Page 321 Section 10 Serial Communication Interface Bit 2    Transmit End Interrupt Enable (TEIE): Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent.
Page 322 Section 10 Serial Communication Interface Serial Status Register (SSR) TDRE RDRF TEND MPBR MPBT Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits.
Page 323 Section 10 Serial Communication Interface Bit 6    Receive Data Register Full (RDRF): Bit 6 indicates that received data is stored in RDR. Bit 6: RDRF Description There is no receive data in RDR (initial value) Clearing conditions: •...
Page 324 Section 10 Serial Communication Interface Bit 4    Framing Error (FER): Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4: FER Description Reception in progress or completed * (initial value) Clearing condition: After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception * Setting condition:...
Page 325 Section 10 Serial Communication Interface Bit 2    Transmit End (TEND): Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2: TEND Description Transmission in progress...
Page 326 Section 10 Serial Communication Interface Bit Rate Register (BRR) BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time.
Page 327 Section 10 Serial Communication Interface OSC (MHz) 4.9152 7.3728 Bit Rate Error Error Error Error (bits/s) –0.26 +0.03 +0.70 +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 1200 +0.16 +0.16 2400 +0.16 +0.16 4800 –2.34 +0.16 9600 –2.34 +0.16   ...
Page 328 Section 10 Serial Communication Interface Notes: 1. The setting should be made so that the error is not more than 1%. 2. The value set in BRR is given by the following equation: × 10 – 1 (64 × 2 ×...
Page 329 Section 10 Serial Communication Interface Table 10.8 shows the maximum bit rate for each frequency. The values shown are for active (high- speed) mode. Table 10.8 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Setting OSC (MHz) Maximum Bit Rate (bits/s) 31250 2.4576 38400...
Page 330 Section 10 Serial Communication Interface Table 10.9 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) ...
Page 331: Operation
Section 10 Serial Communication Interface Note: The value set in BRR is given by the following equation: × 10 – 1 (8 × 2 × B) where Bit rate (bit/s) Baud rate generator BRR setting (0 ≤ N ≤ 255) OSC: Value of φ...
Page 332 Section 10 Serial Communication Interface • Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
Page 333 Section 10 Serial Communication Interface Table 10.12 SMR and SCR3 Settings and Clock Source Selection SCR3 Transmit/Receive Clock Bit 7: Bit 1: Bit 0: Clock CKE1 CKE0 Mode Source Pin Function Asynchronous Internal I/O port (SCK pin not used) mode Outputs clock with same frequency as bit rate External...
Page 334 Section 10 Serial Communication Interface ↑ RSR (reception in progress) RSR (reception completed, transfer) RXD pin RXD pin RDRF ← 1 RDRF = 0 (RXI request when RIE = 1) Figure 10.7 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) ↓...
Page 335: Operation In Asynchronous Mode
Section 10 Serial Communication Interface 10.3.4 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Page 336 Section 10 Serial Communication Interface Table 10.14 shows the 12 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10.14 Data Transfer Formats (Asynchronous Mode) SMR Settings Serial Data Transfer Format and Frame Length STOP...
Page 337 Section 10 Serial Communication Interface Clock: Either an internal clock generated by the baud rate generator or an external clock input at the SCK pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock source selection.
Page 338 Section 10 Serial Communication Interface Figure 10.10 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set clock selection in SCR3. Be sure to Set bits CKE1 clear the other bits to 0. If clock output and CKE0 is selected in asynchronous mode, the clock is output immediately after setting...
Page 339 Section 10 Serial Communication Interface Transmitting: Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR).
Page 340 Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 341 Section 10 Serial Communication Interface Receiving: Figure 10.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, Read bits OER, PER, and FER in the PER, FER in SSR serial status register (SSR) to determine if there is an error.
Page 342 Section 10 Serial Communication Interface If a receive error has Start receive occurred, read bits OER, error processing Overrun error PER, and FER in SSR to processing identify the error, and after carrying out the necessary error processing, ensure OER = 1? that bits OER, PER, and FER are all cleared to 0.
Page 343 Section 10 Serial Communication Interface If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a receive error, bit OER, PER, or FER is set to 1 depending on the kind of error.
Page 344: Operation In Synchronous Mode
Section 10 Serial Communication Interface 10.3.5 Operation in Synchronous Mode In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. SCI3 has separate transmission and reception units, allowing full-duplex communication with a shared clock.
Page 345 Section 10 Serial Communication Interface Clock: Either an internal clock generated by the baud rate generator or an external clock input at the SCK pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3.
Page 346 Section 10 Serial Communication Interface Start Read the serial status register (SSR) and Read bit TDRE check that bit TDRE is set to 1, then write in SSR transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically, the clock is output, and data transmission is started.
Page 347 Section 10 Serial Communication Interface When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock is selected, data is output in synchronization with the input clock. Serial data is transmitted from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7). When the MSB (bit 7) is sent, checks bit TDRE.
Page 348 Section 10 Serial Communication Interface Receiving: Figure 10.18 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER Read bit OER in the serial status register in SSR (SSR) to determine if there is an error.
Page 349 Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Page 350 Section 10 Serial Communication Interface Simultaneous Transmit/Receive: Figure 10.20 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Read bit TDRE Read the serial status register (SSR) and in SSR check that bit TDRE is set to 1, then write transmit data to the transmit data register...
Page 351: Multiprocessor Communication Function
Section 10 Serial Communication Interface Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously with a single instruction. 2.
Page 352 Section 10 Serial Communication Interface Sender Communication line Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle Data transmission cycle (specifying the receiver) (sending data to the receiver...
Page 353 Section 10 Serial Communication Interface Start Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR).
Page 354 Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 355 Section 10 Serial Communication Interface Start Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has Read bits OER occurred, execute receive error processing.
Page 356 Section 10 Serial Communication Interface Start receive error processing Overrun error processing OER = 1? Break? FER = 1? Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing Figure 10.24 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10.25 shows an example of the operation when receiving using the multiprocessor format.
Page 357 Section 10 Serial Communication Interface Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI request RDRF cleared No RXI request operation MPIE cleared to 0 RDR retains to 0 previous state...
Page 358: Interrupts
Section 10 Serial Communication Interface 10.3.7 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.16.
Page 359: Application Notes
Section 10 Serial Communication Interface For further details, see section 3.3, Interrupts. 10.3.8 Application Notes The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR.
Page 360 Section 10 Serial Communication Interface 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD pin directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set.
Page 361 Section 10 Serial Communication Interface 16 clock pulses 8 clock pulses 15 0 15 0 Internal basic clock Receive data Start bit (RXD) Synchronization sampling timing Data sampling timing Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1).
Page 362 Section 10 Serial Communication Interface 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred.
Page 363: Section 11 14-Bit Pwm
Section 11 14-Bit PWM Section 11 14-Bit PWM 11.1 Overview The H8/3644 Group is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 11.1.1 Features Features of the 14-bit PWM are as follows. •...
Page 364: Pin Configuration
Section 11 14-Bit PWM 11.1.3 Pin Configuration Table 11.1 shows the output pin assigned to the 14-bit PWM. Table 11.1 Pin Configuration Name Abbrev. Function PWM output pin Output Pulse-division PWM waveform output 11.1.4 Register Configuration Table 11.2 shows the register configuration of the 14-bit PWM. Table 11.2 Register Configuration Name Abbrev.
Page 365: Pwm Data Registers U And L (Pwdru, Pwdrl)
Section 11 14-Bit PWM Bit 0    Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it is always read as 1. Bit 0: PWCR0 Description * = 2/φ). The conversion period is 16,384/φ, with The input clock is φ/2 (t φ...
Page 366: Operation
Section 11 14-Bit PWM Upon reset, PWDRU and PWDRL are initialized to H'C000. 11.3 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P1 /PWM is designated for PWM output.
Page 367: Section 12 A/D Converter
Section 12 A/D Converter Section 12 A/D Converter 12.1 Overview The H8/3644 Group includes on-chip a resistance-ladder-based successive-approximation analog- to-digital converter, and can convert up to 8 channels of analog input. 12.1.1 Features The A/D converter has the following features. •...
Page 368: Block Diagram
Section 12 A/D Converter 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG Multiplexer ADSR Com- Control logic parator – Reference voltage ADRR IRRAD Legend: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register Figure 12.1 Block Diagram of the A/D Converter Rev.
Page 369: Pin Configuration
Section 12 A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbrev. Function Analog power supply Input Power supply and reference voltage of analog part Analog ground Input Ground and reference voltage of analog part Analog input 0 Input Analog input channel 0...
Page 370: Register Descriptions
Section 12 A/D Converter 12.2 Register Descriptions 12.2.1 A/D Result Register (ADRR) ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to- digital conversion.
Page 371 Section 12 A/D Converter Bit 7    Clock Select (CKS): Bit 7 sets the A/D conversion speed. Conversion Time φ φ φ φ = 8 MHz * φ φ φ φ = 2 MHz φ φ φ φ = 5 MHz Bit 7: CKS Conversion Period 62/φ...
Page 372: A/D Start Register (Adsr)
Section 12 A/D Converter Bits 3 to 0    Channel Select (CH3 to CH0): Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3: Bit 2: Bit 1: Bit 0:...
Page 373: Operation
Section 12 A/D Converter Bit 7    A/D Start Flag (ADSF): Bit 7 controls and indicates the start and end of A/D conversion. Bit 7: ADSF Description Read: Indicates the completion of A/D conversion (initial value) Write: Stops A/D conversion Read: Indicates A/D conversion in progress Write: Starts A/D conversion Bits 6 to 0...
Page 374: Interrupts
Section 12 A/D Converter φ Pin ADTRG (when bit INTEG5 = 0) ADSF A/D conversion Figure 12.2 External Trigger Input Timing 12.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2).
Page 375 Section 12 A/D Converter Figure 12.3 Typical A/D Converter Operation Timing Rev. 6.00 Sep 12, 2006 page 353 of 526 REJ09B0326-0600...
Page 376 Section 12 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRR data Perform A/D conversion? Figure 12.4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software) Rev.
Page 377: Application Notes
Section 12 A/D Converter Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRR data Perform A/D conversion? Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 12.6 Application Notes •...
Page 378 Section 12 A/D Converter Rev. 6.00 Sep 12, 2006 page 356 of 526 REJ09B0326-0600...
Page 379: Section 13 Electrical Characteristics
Section 13 Electrical Characteristics Section 13 Electrical Characteristics 13.1 Absolute Maximum Ratings Table 13.1 lists the absolute maximum ratings. Table 13.1 Absolute Maximum Ratings * Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Programming HD6473644...
Page 380: Electrical Characteristics (Ztat™, Mask Rom Version)
Section 13 Electrical Characteristics 13.2 Electrical Characteristics (ZTAT™, Mask ROM Version) 13.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range 10.0 32.768 •...
Page 381 Section 13 Electrical Characteristics 2. Power supply voltage vs. clock frequency range 16.384 8.192 4.096 • Active (high speed) mode • Subactive mode • Sleep (high speed) mode (except CPU) • Subsleep mode (except CPU) • Watch mode (except CPU) 625.00 39.0625 7.8125...
Page 382 Section 13 Electrical Characteristics 3. Analog power supply voltage vs. A/D converter guaranteed accuracy range Do not exceed the maximum conversion time value. 2.7 * 4.0 4.5 • Active (high speed) mode • Active (medium speed) mode • Sleep (high speed) mode •...
Page 383: Dc Characteristics (Hd6473644)
Section 13 Electrical Characteristics 13.2.2 DC Characteristics (HD6473644) Table 13.2 lists the DC characteristics of the HD6473644. Table 13.2 DC Characteristics = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Applicable Item Symbol...
Page 384 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes RES,  Input low –0.3 0.2 V to INT voltage to IRQ ADTRG, TMIB, TMRIV, TMCIV,  –0.3 0.1 V = 2.7 V to FTCI, FTIA, 5.5 V FTIB, FTIC, including...
Page 385 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes   Output , P1 to P1 = 1.6 mA to P2 voltage to P3 to P5   = 2.7 V to to P7 5.5 V to P8 = 0.4 mA...
Page 386 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes  Active Active (high- 1, 2 OPE1 mode speed) mode current = 5 V, dissipation = 10 MHz   = 2.7 V, 1, 2 = 10 MHz Reference value...
Page 387 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes  Subsleep µA = 2.7 V 1, 2 SUBSP mode 32-kHz crystal current resonator = φ dissipation (φ   Watch µA = 2.7 V 1, 2 WATCH mode...
Page 388 Section 13 Electrical Characteristics Values Item Symbol Unit   Allowable output low Output pins except current (per pin) port 6   Port 6 ∑I   Allowable output low Output pins except current (total) port 6   Port 6 ...
Page 389: Ac Characteristics (Hd6473644)
Section 13 Electrical Characteristics 13.2.3 AC Characteristics (HD6473644) Table 13.3 lists the control signal timing, and tables 13.4 and 13.5 list the serial interface timing of the HD6473644. Table 13.3 Control Signal Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 390 Section 13 Electrical Characteristics Values Applicable Reference Item Symbol Pins Typ Max Unit Test Condition Figure to IRQ   Input pin high width Figure 13.3 to INT subcyc ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV to IRQ ...
Page 391 Section 13 Electrical Characteristics Table 13.4 Serial Interface (SCI1) Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Max Unit Test Condition Figure  ...
Page 392 Section 13 Electrical Characteristics Table 13.5 Serial Interface (SCI3) Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Reference Item Symbol Max Unit Test Condition Figure ...
Page 393: Dc Characteristics (Hd6433644, Hd6433643, Hd6433642, Hd6433641, Hd6433640)
Section 13 Electrical Characteristics 13.2.4 DC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641, HD6433640) Table 13.6 lists the DC characteristics of the HD6433644, the HD6433643, the HD6433642, the HD6433641 and the HD6433640. Table 13.6 DC Characteristics = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated.
Page 394 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes RES,  Input low –0.3 0.2 V to INT voltage to IRQ ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA,  –0.3 0.1 V = 2.5 V to FTIB, FTIC, 5.5 V FTID,...
Page 395 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes –1.0   Output , P1 to P1 –I = 1.5 mA high to P2 voltage to P3 to P5 –0.5   = 2.5 V to to P6 5.5 V to P7...
Page 396 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes   Input All input pins 15.0 f = 1 MHz, except RES capaci- = 0 V, tance = 25°C   15.0   15.0 ...
Page 397 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes  Subsleep µA = 2.5 V 1, 2 SUBSP mode 32-kHz crystal current resonator = φ dissipation (φ   Watch µA = 2.5 V 1, 2 WATCH mode...
Page 398: Ac Characteristics (Hd6433644, Hd6433643, Hd6433642, Hd6433641, Hd6433640)
Section 13 Electrical Characteristics Values Item Symbol Unit   Allowable output low Output pins except current (per pin) port 6   Port 6 ∑I   Allowable output low Output pins except current (total) port 6   Port 6 ...
Page 399 Section 13 Electrical Characteristics Table 13.7 Control Signal Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Min Typ Unit Test Condition Figure  System clock , OSC oscillation frequency...
Page 400 Section 13 Electrical Characteristics Values Applicable Reference Item Symbol Pins Min Typ Unit Test Condition Figure to IRQ   Input pin high width = 2.5 V to 5.5 V Figure 13.3 to INT subcyc ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV...
Page 401 Section 13 Electrical Characteristics Table 13.8 Serial Interface (SCI1) Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Referenc Item Symbol Pins Max Unit Test Condition e Figure ...
Page 402 Section 13 Electrical Characteristics Table 13.9 Serial Interface (SCI3) Timing = 2.5 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Reference Item Symbol Min Max Unit Test Condition Figure ...
Page 403: A/D Converter Characteristics
Section 13 Electrical Characteristics 13.2.6 A/D Converter Characteristics Table 13.10 shows the A/D converter characteristics of the HD6473644, the HD6433644, the HD6433643, the HD6433642, the HD6433641 and the HD6433640. Table 13.10 A/D Converter Characteristics = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 404: Electrical Characteristics (Ztat And R Of The Mask Rom Version)
Section 13 Electrical Characteristics 13.3 Electrical Characteristics (ZTAT and R of the Mask ROM Version) 13.3.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range 16.0 32.768 10.0...
Page 405 Section 13 Electrical Characteristics Power supply voltage vs. clock frequency range 16.384 8.192 4.096 2.7 * 2.7 * • Active (high speed) mode • Subactive mode • Sleep (high speed) mode (except CPU) • Subsleep mode (except CPU) • Watch mode (except CPU) 1000.00 625.00 39.0625...
Page 406 Section 13 Electrical Characteristics 3. Analog power supply voltage vs. A/D converter operating range Do not exceed the maximum conversion time value. 2.7 * • Active (high speed) mode • Active (medium speed) mode • Sleep (high speed) mode • Sleep (medium speed) mode Notes: 1.
Page 407: Dc Characteristics (Hd6473644R)
Section 13 Electrical Characteristics 13.3.2 DC Characteristics (HD6473644R) Table 13.11 lists the DC characteristics of the HD6473644R. Table 13.11 DC Characteristics = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Applicable Item Symbol...
Page 408 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Unit Test Condition Notes RES,  Input low –0.3 0.2 V to INT voltage to IRQ ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA,  –0.3 0.1 V = 2.7 V to FTIB, FTIC, 5.5 V FTID, SCK including...
Page 409 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes –1.0   Output , P1 to P1 –I = 1.5 mA high to P2 voltage to P3 to P5 –0.5   = 2.7 V to to P6 5.5 V to P7...
Page 410 Section 13 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes   Input All input pins 15.0 f = 1 MHz, except RES capaci- = 0 V, tance = 25°C   60.0  ...
Page 411 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Max Unit Test Condition Notes  Subsleep µA = 2.7 V 1, 2 SUBSP mode current 32-kHz crystal dissipation resonator = φ (φ   Watch mode µA = 2.7 V 1, 2 WATCH current...
Page 412 Section 13 Electrical Characteristics Values Item Symbol Unit   Allowable output low Output pins except current (per pin) port 6   Port 6 ∑I   Allowable output low Output pins except current (total) port 6   Port 6 ...
Page 413: Ac Characteristics (Hd6473644R)
Section 13 Electrical Characteristics 13.3.3 AC Characteristics (HD6473644R) Table 13.12 lists the control signal timing, and tables 13.13 and 13.14 list the serial interface timing of the HD6473644R. Table 13.12 Control Signal Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 414 Section 13 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Pin RES low width   = 2.7 V to 5.5 V Figure 13.2 to IRQ   Input pin high level = 2.7 V to 5.5 V Figure 13.3 to INT width subcyc...
Page 415 Section 13 Electrical Characteristics Table 13.13 Serial Interface (SCI1) Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Max Unit Test Condition Figure  ...
Page 416 Section 13 Electrical Characteristics Table 13.14 Serial Interface (SCI3) Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Reference Figure Item Symbol Max Unit Test Condition ...
Page 417: Dc Characteristics (Hd6433644R, Hd6433643R, Hd6433642R, Hd6433641R, Hd6433640R)
Section 13 Electrical Characteristics 13.3.4 DC Characteristics (HD6433644R, HD6433643R, HD6433642R, HD6433641R, HD6433640R) Table 13.15 lists the DC characteristics of the HD6433644R, the HD6433643R, the HD6433642R, the HD6433641R and the HD6433640R. Table 13.15 DC Characteristics = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated.
Page 418 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes RES,  Input low –0.3 0.2 V to INT voltage to IRQ ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA,  –0.3 0.1 V = 2.5 V to FTIB, FTIC, 5.5 V FTID,...
Page 419 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes –1.0   Output , P1 to P1 –I = 1.5 mA high to P2 voltage to P3 to P5 –0.5   = 2.5 V to to P6 5.5 V to P7...
Page 420 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Unit Test Condition Notes   Input All input pins 15.0 f = 1 MHz, except RES capaci- = 0 V, tance = 25°C   15.0   15.0  Active Active (high- 1, 2...
Page 421 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Unit Test Condition Notes  Subsleep µA = 2.5 V 1, 2 SUBSP mode 32-kHz crystal current resonator = φ dissipation (φ   Watch µA = 2.5 V 1, 2 WATCH mode 32-kHz crystal...
Page 422: Ac Characteristics (Hd6433644R, Hd6433643R, Hd6433642R, Hd6433641R, Hd6433640R)
Section 13 Electrical Characteristics Values Item Symbol Unit   Allowable output low Output pins except current (per pin) port 6   Port 6 ∑I   Allowable output low Output pins except current (total) port 6   Port 6 ...
Page 423 Section 13 Electrical Characteristics Table 13.16 Control Signal Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Min Typ Unit Test Condition Figure  System clock , OSC oscillation frequency...
Page 424 Section 13 Electrical Characteristics Values Applicable Reference Item Symbol Pins Min Typ Unit Test Condition Figure to IRQ   Input pin high width = 2.5 V to 5.5 V Figure 13.3 to INT subcyc ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV...
Page 425 Section 13 Electrical Characteristics Table 13.17 Serial Interface (SCI1) Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Max Unit Test Condition Figure  ...
Page 426 Section 13 Electrical Characteristics Table 13.18 Serial Interface (SCI3) Timing = 2.5 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Reference Item Symbol Max Unit Test Condition Figure ...
Page 427: A/D Converter Characteristics
Section 13 Electrical Characteristics 13.3.6 A/D Converter Characteristics Table 13.19 shows the A/D converter characteristics of the HD6473644R, the HD6433644R, the HD6433643R, the HD6433642R, the HD6433641R and the HD6433640R. Table 13.19 A/D Converter Characteristics = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 428: Electrical Characteristics (F-Ztat Version)
Section 13 Electrical Characteristics Electrical Characteristics (F-ZTAT    version) 13.4 13.4.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range 16.0 32.768 10.0...
Page 429 Section 13 Electrical Characteristics 2. Power supply voltage vs. clock frequency range 16.384 8.192 4.096 • Active (high speed) mode • Subactive mode • Sleep (high speed) mode (except CPU) • Subsleep mode (except CPU) • Watch mode (except CPU) 1000.00 625.00 39.0625...
Page 430 Section 13 Electrical Characteristics 3. Analog power supply voltage vs. A/D converter operating range Do not exceed the maximum conversion time value. • Active (high speed) mode • Active (medium speed) mode • Sleep (high speed) mode • Sleep (medium speed) mode Rev.
Page 431: Dc Characteristics (Hd64F3644, Hd64F3643, Hd64F3642A)
Section 13 Electrical Characteristics 13.4.2 DC Characteristics (HD64F3644, HD64F3643, HD64F3642A) Table 13.20 lists the DC characteristics of the HD64F3644, HD64F3643, and HD64F3642A. Table 13.20 DC Characteristics = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Applicable Item...
Page 432 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes RES,  Input low –0.3 0.2 V to INT voltage to IRQ ADTRG, TMIB, TMRIV, TMCIV,  –0.3 0.1 V = 3.0 V to FTCI, FTIA, 5.5 V FTIB, FTIC, including...
Page 433 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Typ Max Unit Test Condition Notes –1.0   Output , P1 to P1 –I = 1.5 mA high to P2 voltage to P3 to P5 –0.5   = 3.0 V to to P6 5.5 V to P7...
Page 434 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Unit Test Condition Notes   Input All input pins 15.0 f = 1 MHz, capaci- except TEST = 0 V, tance = 25°C   , TEST 30.0  Active Active (high- 1, 2 OPE1...
Page 435 Section 13 Electrical Characteristics Values Applicable Item Symbol Pins Unit Test Condition Notes  Subsleep µA = 3.0 V 1, 2 SUBSP mode current 32-kHz crystal dissipation resonator = φ (φ   Watch mode µA = 3.0 V 1, 2 WATCH current 32-kHz crystal...
Page 436 Section 13 Electrical Characteristics Values Item Symbol Unit   Allowable output low Output pins except current (per pin) port 6   Port 6 ∑I   Allowable output low Output pins except current (total) port 6   Port 6 ...
Page 437: Ac Characteristics (Hd64F3644, Hd64F3643, Hd64F3642A)
Section 13 Electrical Characteristics 13.4.3 AC Characteristics (HD64F3644, HD64F3643, HD64F3642A) Table 13.21 lists the control signal timing, and tables 13.22 and 13.23 list the serial interface timing of the HD64F3644, HD64F3643, HD64F3642A. Table 13.21 Control Signal Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 438 Section 13 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Pin RES low width   = 3.0 V to 5.5 V Figure 13.2 to IRQ   Input pin high level = 3.0 V to 5.5 V Figure 13.3 to INT width subcyc...
Page 439 Section 13 Electrical Characteristics Table 13.22 Serial Interface (SCI1) Timing = 4.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Reference Item Symbol Pins Max Unit Test Condition Figure  ...
Page 440 Section 13 Electrical Characteristics Table 13.23 Serial Interface (SCI3) Timing = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Reference Item Symbol Max Unit Test Condition Figure ...
Page 441: A/D Converter Characteristics
Section 13 Electrical Characteristics 13.4.4 A/D Converter Characteristics Table 13.24 shows the A/D converter characteristics of the HD64F3644, HD64F3643, and HD64F3642A. Table 13.24 A/D Converter Characteristics = 3.0 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test...
Page 442: Operation Timing
Section 13 Electrical Characteristics 13.5 Operation Timing Figures 13.1 to 13.6 show timing diagrams. OSC1 Figure 13.1 System Clock Input Timing Figure 13.2 RES RES Low Width Timing to IRQ to INT ADTRG, TMIB, FTIA, FTIB, TMCIV, FTIC, FTID, TMRIV, FTCI, TRGV Figure 13.3 Input Timing Rev.
Page 443 Section 13 Electrical Characteristics Scyc or V or V SCKL SCKH SCKf SCKr Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 13.7. Figure 13.4 SCI1 Input/Output Timing Rev.
Page 444 Section 13 Electrical Characteristics SCKW Scyc Figure 13.5 SCK Input Clock Timing Scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 13.7. Figure 13.6 SCI3 Synchronous Mode Input/Output Timing Rev.
Page 445: Output Load Circuit
Section 13 Electrical Characteristics 13.6 Output Load Circuit 2.4 kΩ Output pin 12 k Ω 30 pF Figure 13.7 Output Load Condition Rev. 6.00 Sep 12, 2006 page 423 of 526 REJ09B0326-0600...
Page 446 Section 13 Electrical Characteristics Rev. 6.00 Sep 12, 2006 page 424 of 526 REJ09B0326-0600...
Page 447: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set Appendix A CPU Instruction Set Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 448 Appendix A CPU Instruction Set Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C #xx:8 → Rd8 MOV.B #xx:8, Rd — — —...
Page 449 Appendix A CPU Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C SP–2 → SP PUSH Rs — — 0 — 6 Rs16 → @SP Rd8+#xx:8 → Rd8 — ADD.B #xx:8, Rd Rd8+Rs8 →...
Page 450 Appendix A CPU Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C Rd16÷Rs8 → Rd16 (RdH: DIVXU.B Rs, Rd — — (5) (6) — — remainder, RdL: quotient) Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd —...
Page 451 Appendix A CPU Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @Rd16) ← 1 BSET #xx:3, @Rd —...
Page 452 Appendix A CPU Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C (#xx:3 of Rd8) → C BLD #xx:3, Rd — — — — — (#xx:3 of @Rd16) → C BLD #xx:3, @Rd —...
Page 453 Appendix A CPU Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation Branching Condition I H N Z V C C⊕(#xx:3 of @Rd16) → C BIXOR #xx:3, @Rd — — — — — C⊕(#xx:3 of @aa:8) → C BIXOR #xx:3, @aa:8 —...
Page 454 Appendix A CPU Instruction Set Addressing Mode/ Condition Code Instruction Length (Bytes) Mnemonic Operation I H N Z V C SP–2 → SP JSR @@aa:8 — — — — — — — 8 PC → @SP PC ← @aa:8 PC ← @SP —...
Page 455: Operation Code Map
Appendix A CPU Instruction Set Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 456 Appendix A CPU Instruction Set Table A.2 Operation Code Map Rev. 6.00 Sep 12, 2006 page 434 of 526 REJ09B0326-0600...
Page 457: Number Of Execution States
Appendix A CPU Instruction Set Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation).
Page 458 Appendix A CPU Instruction Set Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation 2 or 3 * Byte data access Word data access —...
Page 459 Appendix A CPU Instruction Set Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX...
Page 460 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd...
Page 461 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd...
Page 462 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B @Rs, Rd MOV.B @(d:16, Rs), MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, MOV.B Rs, @–Rd MOV.B Rs, @aa:8...
Page 463 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd...
Page 464: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Appendix B Internal I/O Registers Addresses Bit Names Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'F740 H'F741 H'F742 H'F743 H'F744 H'F770 TIER ICIAE ICIBE...
Page 465 Appendix B Internal I/O Registers Bit Names Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'FFA0 SCR1 SNC1 SNC0 MRKON LTCH CKS3 CKS2 CKS1 CKS0 SCI1 H'FFA1 SCSR1 —...
Page 466 Appendix B Internal I/O Registers Bit Names Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'FFBE TCSRW B6WI TCWE B4WI B2WI WDON B0WI WRST Watchdog TCSRWE timer H'FFBF TCW7 TCW6...
Page 467 Appendix B Internal I/O Registers Bit Names Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'FFE0 I/O ports H'FFE1 H'FFE2 H'FFE3 H'FFE4 PCR1 PCR1 PCR1 PCR1 PCR1 —...
Page 468: Functions
Appendix B Internal I/O Registers Functions Register Register Address to which the Name of acronym name register is mapped on-chip supporting module TMC—Timer mode register C H'B4 Timer C numbers Initial bit TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 values Initial value Names of the...
Page 469 Appendix B Internal I/O Registers TIER—Timer interrupt enable register H'F770 Timer X ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — Initial value Read/Write — Timer overflow interrupt enable 0 Interrupt request (FOVI) by OVF is disabled Interrupt request (FOVI) by OVF is enabled Output compare interrupt B enable 0 Interrupt request (OCIB) by OCFB is disabled Interrupt request (OCIB) by OCFB is enabled...
Page 470 Appendix B Internal I/O Registers TCSRX—Timer control/status register X H'F771 Timer X ICFA ICFB ICFC ICFD OCFA OCFB CCLRA Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) Counter clear A 0 FRC is not cleared by compare match A 1 FRC is cleared by compare match A Timer overflow 0 [Clearing condition]...
Page 471 Appendix B Internal I/O Registers FRCH—Free-running counter H H'F772 Timer X FRCH7 FRCH6 FRCH5 FRCH4 FRCH3 FRCH2 FRCH1 FRCH0 Initial value Read/Write Count value FRCL—Free-running counter L H'F773 Timer X FRCL7 FRCL6 FRCL5 FRCL4 FRCL3 FRCL2 FRCL1 FRCL0 Initial value Read/Write Count value OCRAH—Output compare register AH...
Page 472 Appendix B Internal I/O Registers OCRAL—Output compare register AL H'F775 Timer X OCRAL7 OCRAL6 OCRAL5 OCRAL4 OCRAL3 OCRAL2 OCRAL1 OCRAL0 Initial value Read/Write OCRBL—Output compare register BL H'F775 Timer X OCRBL7 OCRBL6 OCRBL5 OCRBL4 OCRBL3 OCRBL2 OCRBL1 OCRBL0 Initial value Read/Write Rev.
Page 473 Appendix B Internal I/O Registers TCRX—Timer control register X H'F776 Timer X IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value Read/Write Clock select Internal clock: φ/2 Internal clock: φ/8 Internal clock: φ/32 Internal clock: rising edge Buffer enable B 0 ICRD is not used as a buffer register for ICRB ICRD is used as a buffer register for OCRB Buffer enable A...
Page 474 Appendix B Internal I/O Registers TOCR—Timer Output compare control register H'F777 Timer X — — — OCRS OLVLA OLVLB Initial value Read/Write — — — Output level B 0 Low level High level Output level A 0 Low level High level Output enable B 0 Output compare B output is disabled Output compare B output is enabled...
Page 475 Appendix B Internal I/O Registers ICRAH—Input capture register AH H'F778 Timer X ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0 Initial value Read/Write ICRAL—Input capture register AL H'F779 Timer X ICRAL7 ICRAL6 ICRAL5 ICRAL4 ICRAL3 ICRAL2 ICRAL1 ICRAL0 Initial value Read/Write ICRBH—Input capture register BH H'F77A...
Page 476 Appendix B Internal I/O Registers FLMCR—Flash memory control register H'FF80 Flash memory (Flash memory version only) — — — Initial value Read/Write — — — Program mode 0 Exit from program mode 1 Transition to program mode Erase mode 0 Exit from erase mode 1 Transition to erase mode Program-verify mode 0 Exit from program-verify mode...
Page 477 Appendix B Internal I/O Registers EBR1—Erase block register 1 H'FF82 Flash memory (Flash memory version only) — — — — Initial value Read/Write — — — — Large block 3 to 0 0 Not selected 1 Selected EBR2—Erase block register 2 H'FF83 Flash memory (Flash memory version only)
Page 478 Appendix B Internal I/O Registers ICRCH—Input capture register CH H'F77C Timer X ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0 Initial value Read/Write ICRCL—Input capture register CL H'F77D Timer X ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0 Initial value Read/Write ICRDH—Input capture register DH H'F77E...
Page 479 Appendix B Internal I/O Registers SCR1—Serial control register 1 H'FFA0 SCI1 SNC1 SNC0 MRKON LTCH CKS3 CKS2 CKS1 CKS0 Initial value Read/Write Clock select (CKS2 to CKS0) Serial Clock Cycle Bit 2 Bit 1 Bit 0 Synchronous Prescaler φ = 5 MHz φ...
Page 480 Appendix B Internal I/O Registers SCSR1—Serial control/status register H'FFA1 SCI1 — ORER — — — MTRF Initial value Read/Write — R/(W) — — — Start flag Read Indicates that transfer is stopped Write Invalid Read Indicates transfer in progress Write Starts a transfer operation TAIL MARK transmit flag 0 Idle state and 8- or -16-bit data transfer in progress...
Page 481 Appendix B Internal I/O Registers SDRU—Serial data register U H'FFA2 SCI1 SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Stores transmit and receive data 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data SDRL—Serial data register L...
Page 482 Appendix B Internal I/O Registers SMR—Serial mode register H'FFA8 SCI3 STOP CKS1 CKS0 Initial value Read/Write Clock select φ clock φ/4 clock φ/16 clock φ/64 clock Multiprocessor mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop bit length 1 stop bit 2 stop bits Parity mode Even parity...
Page 483 Appendix B Internal I/O Registers BRR—Bit rate register H'FFA9 SCI3 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write Rev. 6.00 Sep 12, 2006 page 461 of 526 REJ09B0326-0600...
Page 484 Appendix B Internal I/O Registers SCR3—Serial control register 3 H'FFAA SCI3 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable Description Bit 1 Bit 0 CKE1 CKE0 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous...
Page 485 Appendix B Internal I/O Registers TDR—Transmit data register H'FFAB SCI3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write Data for transfer to TSR Rev. 6.00 Sep 12, 2006 page 463 of 526 REJ09B0326-0600...
Page 486 Appendix B Internal I/O Registers SSR—Serial status register H'FFAC SCI3 TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmit end...
Page 487 Appendix B Internal I/O Registers RDR—Receive data register H'FFAD SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write TMA—Timer mode register A H'FFB0 Timer A TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value Read/Write — Clock output select Internal clock select φ/32...
Page 488 Appendix B Internal I/O Registers TCA—Timer counter A H'FFB1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write Count value TMB1—Timer mode register B1 H'FFB2 Timer B1 TMB17 — — — — TMB12 TMB11 TMB10 Initial value Read/Write —...
Page 489 Appendix B Internal I/O Registers TCB1—Timer counter B1 H'FFB3 Timer B1 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 Initial value Read/Write Count value TLB1—Timer load register B1 H'FFB3 Timer B1 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10 Initial value Read/Write Reload value Rev.
Page 490 Appendix B Internal I/O Registers TCRV0—Timer control register V0 H'FFB8 Timer V CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 Description CKS2 CKS1 CKS0 ICKS0 —...
Page 491 Appendix B Internal I/O Registers TCSRV—Timer control/status register V H'FFB9 Timer V CMFB CMFA — Initial value Read/Write R/(W) R/(W) R/(W) — Output select No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A Output select No change at compare match B...
Page 492 Appendix B Internal I/O Registers TCORA—Time constant register A H'FFBA Timer V TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 Initial value Read/Write TCORB—Time constant register B H'FFBB Timer V TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 Initial value Read/Write TCNTV—Timer counter V H'FFBC...
Page 493 Appendix B Internal I/O Registers TCRV1—Timer control register V1 H'FFBD Timer V — — — TVEG1 TVEG0 TRGE — ICKS0 Initial value Read/Write — — — — Internal clock select Selects the TCNTV clock source, with bits CKS2 to CKS0 in TCRV0 TRGV input enable 0 TCNTV counting is not triggered by input at the TRGV pin, and does not stop when TCNTV is cleared by compare match...
Page 494 Appendix B Internal I/O Registers TCSRW—Timer control/status register W H'FFBE Watchdog timer B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST Initial value Read/Write R/(W) R/(W) R/(W) R/(W) Watchdog timer reset 0 [Clearing conditions] • Reset by RES pin • When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit...
Page 495 Appendix B Internal I/O Registers TCW—Timer counter W H'FFBF Watchdog timer TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value Rev. 6.00 Sep 12, 2006 page 473 of 526 REJ09B0326-0600...
Page 496 Appendix B Internal I/O Registers AMR—A/D mode register H'FFC4 A/D converter TRGE — — Initial value Read/Write — — Channel select Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected Reserved Reserved Reserved Reserved * Don’t care External trigger select 0 Disables start of A/D conversion by exter al trigger 1 Enables start of A/D conversion by rising or falling edge...
Page 497 Appendix B Internal I/O Registers ADRR—A/D result register H'FFC5 A/D converter ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write A/D conversion result ADSR—A/D start register H'FFC6 A/D converter ADSF —...
Page 498 Appendix B Internal I/O Registers PWCR—PWM control register H'FFD0 14-bit PWM — — — — — — — PWCR0 Initial value Read/Write — — — — — — — Clock select 0 The input clock is φ/2 (tφ = 2/φ). The conversion period is 16,384/φ, with a minimum modulation width of 1/φ.
Page 499 Appendix B Internal I/O Registers PDR1—Port data register 1 H'FFD4 I/O ports — — — Initial value Read/Write — — — PDR2—Port data register 2 H'FFD5 I/O ports — — — — — Initial value Read/Write — — — — —...
Page 500 Appendix B Internal I/O Registers PDR7—Port data register 7 H'FFDA I/O ports — — — Initial value Read/Write — — — PDR8—Port data register 8 H'FFDB I/O ports Initial value Read/Write PDR9—Port data register 9 H'FFDC I/O ports — — —...
Page 501 Appendix B Internal I/O Registers PCR1—Port control register 1 H'FFE4 I/O ports PCR1 PCR1 PCR1 PCR1 — — — PCR1 Initial value Read/Write — — — Port 1 input/output select 0 Input pin 1 Output pin PCR2—Port control register 2 H'FFE5 I/O ports —...
Page 502 Appendix B Internal I/O Registers PCR5—Port control register 5 H'FFE8 I/O ports PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 Initial value Read/Write Port 5 input/output select 0 Input pin 1 Output pin PCR6—Port control register 6 H'FFE9 I/O ports PCR6 PCR6 PCR6...
Page 503 Appendix B Internal I/O Registers PCR8—Port control register 8 H'FFEB I/O ports PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 Initial value Read/Write Port 8 input/output select 0 Input pin 1 Output pin PCR9—Port control register 9 H'FFEC I/O ports —...
Page 504 Appendix B Internal I/O Registers PUCR5—Port pull-up control register 5 H'FFEF I/O ports PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write SYSCR1—System control register 1 H'FFF0 System control SSBY STS2 STS1 STS0 LSON — Initial value Read/Write —...
Page 505 Appendix B Internal I/O Registers SYSCR2—System control register 2 H'FFF1 System control — — — NESEL DTON MSON Initial value Read/Write — — — Subactive mode clock select φ /8 φ /4 φ /2 Don’t care Medium speed on flag 0 •...
Page 506 Appendix B Internal I/O Registers IEGR1—Interrupt edge select register 1 H'FFF2 System control — — — — IEG3 IEG2 IEG1 IEG0 Initial value Read/Write — — — — edge select 0 Falling edge of IRQ pin input is detected Rising edge of IRQ pin input is detected edge select 0 Falling edge of IRQ...
Page 507 Appendix B Internal I/O Registers IEGR2—Interrupt edge select register 2 H'FFF3 System control INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0 Initial value Read/Write to INT edge select 0 Falling edge of INT pin input is detected Rising edge of INT pin input is detected (n = 4 to 0) edge select...
Page 508 Appendix B Internal I/O Registers IENR1—Interrupt enable register 1 H'FFF4 System control IENTB1 IENTA — — IEN3 IEN2 IEN1 IEN0 Initial value Read/Write — — to IRQ interrupt enable 0 Disables IRQ3 to IRQ interrupt requests Enables IRQ3 to IRQ interrupt requests Timer A interrupt enable 0 Disables timer A interrupt requests...
Page 509 Appendix B Internal I/O Registers IENR2—Interrupt enable register 2 H'FFF5 System control IENDT IENAD — IENS1 — — — — Initial value Read/Write — — — — — SCI1 interrupt enable 0 Disables SCI1 interrupt requests Enables SCI1 interrupt requests A/D converter interrupt enable 0 Disables A/D converter interrupt requests Enables A/D converter interrupt requests...
Page 510 Appendix B Internal I/O Registers IRR1—Interrupt request register 1 H'FFF7 System control IRRTB1 IRRTA — — IRRI3 IRRI2 IRRI1 IRRI0 Initial value Read/Write — — to IRQ interrupt request flag 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 1 [Setting condition] When pin IRQn is set for interrupt input and the designated signal edge is input...
Page 511 Appendix B Internal I/O Registers IRR2—Interrupt request register 2 H'FFF8 System control IRRDT IRRAD — IRRS1 — — — — Initial value Read/Write — — — — — SCI1 interrupt request flag 0 [Clearing condition] When IRRS1 = 1, it is cleared by writing 0 1 [Setting condition] When an SCI1 transfer is completed A/D converter interrupt request flag...
Page 512 Appendix B Internal I/O Registers IRR3—Interrupt request register 3 H'FFF9 System control INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0 Initial value Read/Write to INT interrupt request flag 0 [Clearing condition] When INTF = 1, it is cleared by writing 0 1 [Setting condition] When the designated signal edge is input at pin INT (n = 7 to 0)
Page 513 Appendix B Internal I/O Registers PMR1—Port mode register 1 H'FFFC I/O ports IRQ3 IRQ2 IRQ1 — — — TMOW Initial value Read/Write — — — /TMOW pin function switch 0 Functions as P1 I/O pin Functions as TMOW output pin /PWM pin function switch 0 Functions as P1 I/O pin...
Page 514 Appendix B Internal I/O Registers PMR3—Port mode register 3 H'FFFD I/O ports — — — — — SCK1 Initial value Read/Write — — — — — /SCK pin function switch 0 Functions as P3 I/O pin Functions as SCK I/O pin pin function switch 0 Functions as P3 I/O pin...
Page 515: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Block Diagrams of Port 1 (low level during reset and in standby mode) PUCR1 PMR1 Internal PDR1 data bus PCR1 n–4 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1...
Page 516 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) PUCR1 PMR1 Internal PDR1 data bus PCR1 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (b) Port 1 Block Diagram (Pin P1 Rev.
Page 517 Appendix C I/O Port Block Diagrams module (low level during reset and in standby mode) PUCR1 PMR1 Internal PDR1 data bus PCR1 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (c) Port 1 Block Diagram (Pin P1 Rev.
Page 518 Appendix C I/O Port Block Diagrams Timer A module TMOW (low level during reset and in standby mode) PUCR1 PMR1 Internal PDR1 data bus PCR1 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (d) Port 1 Block Diagram (Pin P1...
Page 519: Block Diagrams Of Port 2
Appendix C I/O Port Block Diagrams Block Diagrams of Port 2 PMR7 SCI3 module Internal PDR2 data bus PCR2 Legend: PDR2: Port data register 2 PCR2: Port control register 2 PMR7: Port mode register 7 Figure C.2 (a) Port 2 Block Diagram (Pin P2 Rev.
Page 520 Appendix C I/O Port Block Diagrams SCI3 module PDR2 Internal PCR2 data bus Legend: PDR2: Port data register 2 PCR2: Port control register 2 Figure C.2 (b) Port 2 Block Diagram (Pin P2 Rev. 6.00 Sep 12, 2006 page 498 of 526 REJ09B0326-0600...
Page 521 Appendix C I/O Port Block Diagrams SCI3 module SCKIE SCKOE SCKO SCKI PDR2 Internal data bus PCR2 Legend: PDR2: Port data register 2 PCR2: Port control register 2 Figure C.2 (c) Port 2 Block Diagram (Pin P2 Rev. 6.00 Sep 12, 2006 page 499 of 526 REJ09B0326-0600...
Page 522: Block Diagrams Of Port 3
Appendix C I/O Port Block Diagrams Block Diagrams of Port 3 SCI1 module (low level during PMR7 reset and in standby mode) PUCR3 PMR3 Internal PDR3 data bus PCR3 Legend: PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PMR7:...
Page 523 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) PUCR3 PMR3 Internal PDR3 data bus PCR3 SCI1 module Legend: PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (b) Port 3 Block Diagram (Pin P3 Rev.
Page 524 Appendix C I/O Port Block Diagrams SCI1 module (low level during CKS3 reset and in standby mode) SCK0 SCK1 PUCR3 PMR3 PDR3 PCR3 Legend: PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (c) Port 3 Block Diagram (Pin P3 Rev.
Page 525: Block Diagrams Of Port 5
Appendix C I/O Port Block Diagrams Block Diagrams of Port 5 (low level during reset and in standby mode) PUCR5 PDR5 PCR5 module Legend: PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5 Note: n = 7, 4 to 0 Figure C.4 (a) Port 5 Block Diagram (Pins P5...
Page 526 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Timer B1 PUCR5 module TMIB PDR5 PCR5 module Legend: PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5 Figure C.4 (b) Port 5 Block Diagram (Pin P5 Rev.
Page 527 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) PUCR5 module ADTRG PDR5 PCR5 module Legend: PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5 Figure C.4 (c) Port 5 Block Diagram (Pin P5 Rev.
Page 528: Block Diagram Of Port 6
Appendix C I/O Port Block Diagrams Block Diagram of Port 6 (low level during reset and in standby mode) PDR6 Internal data bus PCR6 Legend: PDR6: Port data register 6 PCR6: Port control register 6 Note: n = 7 to 0 Figure C.5 Port 6 Block Diagram (Pins P6 to P6 Rev.
Page 529: Block Diagrams Of Port 7
Appendix C I/O Port Block Diagrams Block Diagrams of Port 7 (low level during reset and in standby mode) Internal PDR7 data bus PCR7 Legend: PDR7: Port data register 7 PCR7: Port control register 7 Note: n = 7 or 3 Figure C.6 (a) Port 7 Block Diagram (Pins P7 and P7 Rev.
Page 530 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Timer V module TMOV PDR7 Internal PCR7 data bus Legend: PDR7: Port data register 7 PCR7: Port control register 7 Figure C.6 (b) Port 7 Block Diagram (Pin P7 Rev.
Page 531 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Internal PDR7 data bus PCR7 Timer V module TMCIV Legend: PDR7: Port data register 7 PCR7: Port control register 7 Figure C.6 (c) Port 7 Block Diagram (Pin P7 Rev.
Page 532 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Internal PDR7 data bus PCR7 Timer V module TMRIV Legend: PDR7: Port data register 7 PCR7: Port control register 7 Figure C.6 (d) Port 7 Block Diagram (Pin P7 Rev.
Page 533: Block Diagrams Of Port 8
Appendix C I/O Port Block Diagrams Block Diagrams of Port 8 (low level during reset and in standby mode) Internal PDR8 data bus PCR8 Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (a) Port 8 Block Diagram (Pin P8 Rev.
Page 534 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Internal PDR8 data bus PCR8 Timer X module FTID Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (b) Port 8 Block Diagram (Pin P8 Rev.
Page 535 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Internal PDR8 data bus PCR8 Timer X module FTIC Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (c) Port 8 Block Diagram (Pin P8 Rev.
Page 536 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Internal PDR8 data bus PCR8 Timer X module FTIB Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (d) Port 8 Block Diagram (Pin P8 Rev.
Page 537 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Internal PDR8 data bus PCR8 Timer X module FTIA Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (e) Port 8 Block Diagram (Pin P8 Rev.
Page 538 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Timer X module FTOB PDR8 Internal PCR8 data bus Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (f) Port 8 Block Diagram (Pin P8 Rev.
Page 539 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Timer X module FTOA PDR8 Internal PCR8 data bus Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (g) Port 8 Block Diagram (Pin P8 Rev.
Page 540 Appendix C I/O Port Block Diagrams (low level during reset and in standby mode) Internal PDR8 data bus PCR8 Timer X module FTCI Legend: PDR8: Port data register 8 PCR8: Port control register 8 Figure C.7 (h) Port 8 Block Diagram (Pin P8 Rev.
Page 541: Block Diagram Of Port 9
Appendix C I/O Port Block Diagrams Block Diagram of Port 9 (low level during reset and in standby mode) Internal PDR9 data bus PCR9 Legend: PDR9: Port data register 9 PCR9: Port control register 9 Note: n = 4 to 0 Figure C.8 Port 9 Block Diagram (Pins P9 to P9 Rev.
Page 542: Block Diagram Of Port B
Appendix C I/O Port Block Diagrams Block Diagram of Port B Internal data bus A/D module AMR3 to AMR0 Note: n = 7 to 0 Figure C.9 Port B Block Diagram (Pins PB to PB Rev. 6.00 Sep 12, 2006 page 520 of 526 REJ09B0326-0600...
Page 543: Appendix D Port States In The Different Processing States
Appendix D Port States in the Different Processing States Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active to P1 High Retained Retained High Retained Functions Functions impedance * impedance to P2...
Page 544 Appendix E Product Code Lineup Appendix E Product Code Lineup Table E.1 Product Lineup Package Product Type Product Code Mark Code (Package Code) H8/3644 ZTAT Standard HD6473644H HD6473644H 64-pin QFP (FP-64A) version products HD6473644RH HD6473644P HD6473644P 64-pin SDIP (DP-64S) HD6473644RP HD6473644W HD6473644W 80-pin TQFP (TFP-80C)
Page 545 Appendix E Product Code Lineup Package Product Type Product Code Mark Code (Package Code) H8/3642 FLASH Standard HD64F3642AH HD64F3642AH 64-pin QFP (FP-64A) products HD64F3642AP HD64F3642AP 64-pin SDIP (DP-64S) HD64F3642AW HD64F3642AW 80-pin TQFP (TFP-80C) Mask ROM HD6433642H HD6433642(***)H 64-pin QFP (FP-64A) version HD6433642RH HD6433642P...
Page 546 Appendix F Package Dimensions Appendix F Package Dimensions The package dimension that is shown in the Package Data Book has priority. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP64-14x14-0.80 PRQP0064GB-A FP-64A/FP-64AV 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
Page 547 Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-SDIP64-17x57.6-1.78 PRDP0064BB-A DP-64S/DP-64SV 8.8g Dimension in Millimeters Reference Symbol Min Nom Max 19.05 57.6 58.5 17.0 18.6 5.08 0.51 0.38 0.48 0.58 0.20 0.25 0.36 θ 0˚ 15˚...
Page 548 Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP80-12x12-0.50 PTQP0080KC-A TFP-80C/TFP-80CV 0.4g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Terminal cross section Symbol 1.00 13.8 14.0...
Page 549 Publication Date: 1st Edition, September 1999 Rev.6.00, September 12, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 550 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 551 H8/3644 Group, H8/3644R Group H8/3644 F-ZTAT , H8/3643 F-ZTAT H8/3642A F-ZTAT User’s Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0326-0600...

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