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9.2.5
Timer Interrupt Status Register B (TISRB)
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables general register compare match and input capture interrupt requests.
Bit
7
1
Initial value
Read/Write
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRB is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables
the interrupt requested by the IMFB2 flag when IMFB2 is set to 1.
Bit 6
IMIEB2
Description
0
IMIB2 interrupt requested by IMFB2 flag is disabled
1
IMIB2 interrupt requested by IMFB2 flag is enabled
6
5
IMIEB2
IMIEB1
IMIEB0
0
0
R/W
R/W
R/W
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
4
3
2
IMFB2
1
0
0
R/(W)*
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
Reserved bit
Rev. 4.00 Jan 26, 2006 page 345 of 938
Section 9 16-Bit Timer
1
0
IMFB1
IMFB0
0
0
R/(W)*
R/(W)*
(Initial value)
REJ09B0276-0400
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