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Section 6 Bus Controller
Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate
in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are
initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to
software standby mode.
Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T
state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
3
performed. See Figure 6.39.
T
T
T
1
2
3
φ
RTCNT address
Address bus
Internal write signal
Counter clear signal
RTCNT
N
H'00
Figure 6.39 Contention between RTCNT Write and Clear
Rev. 4.00 Jan 26, 2006 page 192 of 938
REJ09B0276-0400
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