Renesas H8/3067 Series User Manual page 36

Section 1 Overview
Type Symbol
Address A to A
23 0
bus
Data bus D to D
15 0
CS
Bus to
7
CS
control
0
AS
RD
HWR
LWR
Bus
control
WAIT
RFSH
DRAM
interface
CS
to
2
CS
5
RD
HWR
UCAS
LWR
LCAS
DREQ
DMA ,
1
DREQ
controller
0
(DMAC)
TEND
,
1
TEND
0
Rev. 4.00 Jan 26, 2006 page 12 of 938
REJ09B0276-0400
Pin No.
PRQP
0100KA-A
PTQP PRQP
0100KA-A 0100JE-B I/O
97 to 100, 99, 100, 1,
56 to 45, 2, 58 to 47,
43 to 36 45 to 38
34 to 23, 36 to 25,
21 to 18 23 to 20
2 to 5, 4 to 7,
88 to 91 90 to 93
69 71
70 72
71 73
72 74
58 60
87 89
89, 88, 5, 4 91, 90, 7, 6 Output Row address strobe RAS
70 72
71 73
6 8
72 74
7 9
5, 3 7, 5
94, 93 96, 95
Name and Function
Output Address bus: Outputs address signals
Input/ Data bus: Bidirectional data bus
output
Output Chip select: Select signals for areas 7 to 0
Output Address strobe: Goes low to indicate
valid address output on the address bus
Output Read: Goes low to indicate reading from
the external address space
Output High write: Goes low to indicate writing to
the external address space; indicates valid
data on the upper data bus (D
Output Low write: Goes low to indicate writing to
the external address space; indicates valid
data on the lower data bus (D
Input Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
Output Refresh: Indicates a refresh cycle
strobe signal for DRAM
Output Write enable WE
DRAM
Output Upper column address strobe UCAS
Column address strobe signal for DRAM
Output Lower column address strobe LCAS
Column address strobe signal for DRAM
Input DMA request 1 and 0: DMAC activation
requests
Output Transfer end 1 and 0: These signals
indicate that the DMAC has ended a data
transfer
to D
15
to D
7 0
RAS: Row address
RAS RAS
WE: Write enable signal for
WE WE
UCAS:
UCAS UCAS
LCAS:
LCAS LCAS
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