Table of Contents
Advertisement
14.2.3
Serial Mode Register (SMR)
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a
modification to the function of bits 1 and 0 in the serial control register (SCR).
Bit
7
GM
Initial value
0
Read/Write
R/W
Bit 7—GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting
this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the
TEND flag that indicates completion of transmission, and the type of clock output used. The
details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in
the serial control register (SCR).
Bit 7
GM
Description
0
Normal smart card interface mode operation
The TEND flag is set 12.5 etu after the beginning of the start bit.
Clock output on/off control only.
1
GSM mode smart card interface mode operation
The TEND flag is set 11.0 etu after the beginning of the start bit.
Clock output on/off and fixed-high/fixed-low control.
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 13.2.5,
Serial Mode Register (SMR).
6
5
CHR
PE
O/E
0
0
R/W
R/W
R/W
Section 14 Smart Card Interface
4
3
2
STOP
MP
0
0
0
R/W
R/W
Rev. 4.00 Jan 26, 2006 page 549 of 938
1
0
CKS1
CKS0
0
0
R/W
R/W
(Initial value)
REJ09B0276-0400
Advertisement
Table of Contents
