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Bits 5 to 3—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be
input to RTCNT from among 7 clocks obtained by dividing the system clock (φ). When the input
clock is selected with bits CKS2 to CKS0, RTCNT begins counting up.
Bit 5
Bit 4
Bit 3
CKS2
CKS1
CKS0 Description
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 1.
6.2.10
Refresh Timer Counter (RTCNT)
7
Bit
Initial value
0
Read/Write
R/W
RTCNT is an 8-bit readable/writable up-counter.
RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When
RTCNT matches RTCOR (compare match), the CMF flag in RTMCSR is set to 1 and RTCNT is
cleared to H'00. If the RCYCE bit in DRCRB is set to 1 at this time, a refresh cycle is started.
Also, if the CMIE bit in RTMCSR is set to 1, a compare match interrupt (CMI) is generated.
RTCNT is initialized to H'00 by a reset and in standby mode.
Count operation halted
φ/2 used as counter clock
φ/8 used as counter clock
φ/32 used as counter clock
φ/128 used as counter clock
φ/512 used as counter clock
φ/2048 used as counter clock
φ/4096 used as counter clock
6
5
0
0
R/W
R/W
4
3
0
0
R/W
R/W
Rev. 4.00 Jan 26, 2006 page 141 of 938
Section 6 Bus Controller
(Initial value)
2
1
0
0
R/W
R/W
REJ09B0276-0400
0
0
R/W
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