Renesas H8/3067 Series User Manual page 163

Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE Description
0 Refresh cycles disabled
1 DRAM refresh cycles enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (TP) is to
be used for DRAM read/write cycles and CAS-before-RAS refresh cycles.
The setting of this bit does not affect the self-refresh function.
Bit 2
TPC Description
0 1-state precharge cycle inserted
1 2-state precharge cycle inserted
RAS-CAS CAS Wait (RCW): Controls wait state (Trw) insertion between T
RAS RAS CAS CAS
Bit 1—RAS
read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1
RCW Description
0 Wait state (Trw) insertion disabled
1 One wait state (Trw) inserted
Bit 0—Refresh Cycle Wait Control (RLW): Controls wait state (T
RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0
RLW Description
0 Wait state (T
1 One wait state (T
) insertion disabled
RW
) inserted
RW
Section 6 Bus Controller
) insertion for CAS-before-
RW
Rev. 4.00 Jan 26, 2006 page 139 of 938
(Initial value)
(Initial value)
and T in DRAM
r c1
(Initial value)
(Initial value)
REJ09B0276-0400