Renesas H8/3067 Series User Manual page 484

Renesas 16-bit single-chip microcomputer
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Section 11 Programmable Timing Pattern Controller (TPC)
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before
the next compare match B occurs.
Figure 11.10 shows the timing relationships.
Compare
match A
Compare
match B
NDR
DR
Figure 11.10 Non-Overlapping Operation and NDR Write Timing
Rev. 4.00 Jan 26, 2006 page 460 of 938
REJ09B0276-0400
NDR write
0 output
0/1 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
NDR write
0 output
0/1 output
Write to NDR
in this interval
Do not write
to NDR in this
interval

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