Renesas H8/3067 Series User Manual page 373

Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the
OVF1 flag when OVF1 is set to 1.
Bit 5
OVIE1 Description
0 OVI1 interrupt requested by OVF1 flag is disabled
1 OVI1 interrupt requested by OVF1 flag is enabled
Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the
OVF0 flag when OVF0 is set to 1.
Bit 4
OVIE0 Description
0 OVI0 interrupt requested by OVF0 flag is disabled
1 OVI0 interrupt requested by OVF0 flag is enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Overflow Flag 2 (OVF2): This status flag indicates TCNT2 overflow or underflow.
Bit 2
OVF2 Description
0 [Clearing condition]
Read OVF2 when OVF2 =1, then write 0 in OVF2.
1 [Setting condition]
TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF.
Note: TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow occurs
only when channel 2 operates in phase counting mode (MDF = 1 in TMDR).
Bit 1—Overflow Flag 1 (OVF1): This status flag indicates TCNT1 overflow.
Bit 1
OVF1 Description
0 [Clearing condition]
Read OVF1 when OVF1 =1, then write 0 in OVF1.
1 [Setting condition]
TCNT1 overflowed from H'FFFF to H'0000.
Section 9 16-Bit Timer
Rev. 4.00 Jan 26, 2006 page 349 of 938
(Initial value)
(Initial value)
(Initial value)
(Initial value)
REJ09B0276-0400