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3.2.2
System Control Register (SYSCR)
SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for
NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables
the on-chip RAM address space.
Initial
Bit
Bit Name
Value
7, 6
—
All 0
5
INTM1
0
4
INTM0
0
3
XRST
1
2
NMIEG
0
R/W
Description
R/W
Reserved
The initial value should not be changed.
R
Interrupt Control Select Mode 1 and 0
R/W
These bits select the interrupt control mode of the
interrupt controller.
For details on the interrupt control modes, see section
6.6, Interrupt Control Modes and Interrupt Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
R
Reset Source
Indicates the reset source. A reset is caused by a pin
reset, power-on reset or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer overflows
1: A reset is caused by a pin and the power-on.
R/W
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Section 3 MCU Operating Modes
Rev. 1.00 May 09, 2008 Page 67 of 954
REJ09B0462-0100
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