Table of Contents
Advertisement
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
Description
0
The DEND interrupt requested by DTE is disabled
1
The DEND interrupt requested by DTE is enabled
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.
Bit 2
Bit 1
Bit 0
DTS2
DTS1
DTS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: See section 7.3.4, Data Transfer Control Registers (DTCR).
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 7.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
Description
Compare match/input capture A interrupt from 16-bit timer
channel 0
Compare match/input capture A interrupt from 16-bit timer channel 1
Compare match/input capture A interrupt from 16-bit timer channel 2
Conversion-end interrupt from A/D converter
Transmit-data-empty interrupt from SCI channel 0
Receive-data-full interrupt from SCI channel 0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
Section 7 DMA Controller
Rev. 4.00 Jan 26, 2006 page 219 of 938
(Initial value)
(Initial value)
REJ09B0276-0400
Advertisement
Table of Contents
