Section 10 8-Bit Timers
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Rev. 4.00 Jan 26, 2006 page 412 of 938
REJ09B0276-0400