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16 bits. A
to A
are valid when 0 is written in bits 7 to 5 of the bus release control register
23
21
(BRCR). (In this mode A
3.4.4
Mode 4
Ports 1, 2, and 5 and part of port A function as address pins A
maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to
8 bits. A
to A
are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A
23
21
used for address output.)
3.4.5
Mode 5
Ports 1, 2, and 5 and part of port A can function as address pins A
maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1. For A
mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-
bit access in ABWCR, the bus mode switches to 16 bits.
3.4.6
Mode 6
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 6 supports a maximum address space of 64 kbytes.
3.4.7
Mode 7
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 7 supports a 1-Mbyte address space.
is always used for address output.)
20
to A
output, write 0 in bits 7 to 4 of BRCR. The initial bus
23
20
Section 3 MCU Operating Modes
to A
, permitting access to a
23
0
to A
, permitting access to a
23
0
Rev. 4.00 Jan 26, 2006 page 69 of 938
REJ09B0276-0400
is always
20
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