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Section 11 Programmable Timing Pattern Controller (TPC)
11.2.3
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
7
PB
DDR
7
Initial value
0
Read/Write
W
Port B is multiplexed with pins TP
be set to 1. For further information about PBDDR, see section 8.12, Port B.
11.2.4
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
7
PB
Initial value
0
Read/Write
R/(W)*
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 8.12, Port B.
Rev. 4.00 Jan 26, 2006 page 440 of 938
REJ09B0276-0400
6
5
PB
DDR
PB
DDR
6
5
0
0
W
W
to TP
. Bits corresponding to pins used for TPC output must
15
8
6
5
PB
PB
7
6
5
0
0
R/(W)*
R/(W)*
4
3
PB
DDR
PB
DDR
PB
4
3
0
0
W
W
Port B direction 7 to 0
These bits select input or
output for port B pins
4
3
PB
PB
4
3
0
0
R/(W)*
R/(W)*
R/(W)*
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
2
1
0
DDR
PB
DDR
PB
2
1
0
0
0
0
W
W
W
2
1
0
PB
PB
PB
2
1
0
0
0
R/(W)*
R/(W)*
DDR
0
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