Renesas H8/3067 Series User Manual page 63

Renesas 16-bit single-chip microcomputer
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Instruction Size*
EXTS
W/L
EXTU
W/L
Note: * Size refers to the operand size.
B:
Byte
W: Word
L:
Longword
Table 2.5
Logic Operation Instructions
Instruction Size*
AND
B/W/L
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Note: * Size refers to the operand size.
B:
Byte
W: Word
L:
Longword
Function
Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Function
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another general
register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another general
register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and another
general register or immediate data.
¬ Rd → Rd
Takes the one's complement (logical complement) of general register
contents.
Rev. 4.00 Jan 26, 2006 page 39 of 938
REJ09B0276-0400
Section 2 CPU

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